US2022384630A1PendingUtilityA1

High electron mobility transistor (hemt) with a back barrier layer

Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Oct 29, 2020Filed: Aug 8, 2022Published: Dec 1, 2022
Est. expiryOct 29, 2040(~14.3 yrs left)· nominal 20-yr term from priority
H10P 50/646H10P 14/3416H10P 14/3216H10P 14/2926H10P 14/2905H10P 14/36H10P 14/3251H01L 29/66462H01L 21/02433H01L 21/02458H01L 29/205H01L 21/02381H01L 29/2003H01L 21/0254H01L 21/30612H01L 29/7786H10D 64/256H10D 62/8503H10D 62/824H10D 30/015H10D 62/343H10D 30/47H10D 30/475H10D 30/4732H10D 62/124
68
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AIN).

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for manufacturing a High Electron Mobility Transistor, comprising:
 forming a first portion of a Gallium Nitride (GaN) layer;   depositing a back barrier layer on the first portion of the GaN layer;   forming a second portion of the GaN layer over the back barrier layer;   depositing a front barrier layer on the second portion of the GaN layer; and   forming a source electrode, a drain electrode and a gate electrode on the front barrier layer,   wherein the back barrier layer comprises Aluminum Nitride (AlN), and where a 2-Dimensional Electron Gas (2-DEG) in the second portion of the GaN layer at a first interface between the second portion of the GaN layer and the front barrier layer.   
     
     
         2 . The method of  claim 1 , wherein the front barrier layer comprises Aluminum Gallium Nitride (Al x Ga 1-x N), and wherein 0≤x≤1. 
     
     
         3 . The method of  claim 1 , wherein a first thickness of the second portion of the GaN layer is in a range of 25 and 350 nanometers and a second thickness of the GaN layer is in a range of 300 and 1500 nanometers. 
     
     
         4 . The method of  claim 1 , wherein a third thickness of the back barrier layer is in a range of 0.5 and 10 nanometers. 
     
     
         5 . The method of  claim 1 , wherein electrons in the 2-DEG in the GaN layer at the first interface is blocked by a second interface between the first portion of the GaN layer and the back barrier layer. 
     
     
         6 . The method of  claim 1 , further comprising:
 prior to the forming a first portion of a GaN layer,   preparing a buffer layer on a Silicon (Si) substrate, wherein the buffer layer comprises AlyGal-yN and the Si substrate has a surface orientation of <111>; and   forming a conductive GaN layer on the buffer layer.   
     
     
         7 . A method of making a semiconductor device, comprising:
 forming a Gallium Nitride (GaN) layer;   forming a front barrier layer over the GaN layer;   forming a source electrode, a drain electrode and a gate electrode over the front barrier layer;   providing a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and   forming a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).   
     
     
         8 . The method of  claim 7 , wherein the front barrier layer comprises Aluminum Gallium Nitride (Al x Ga 1-x N), and wherein 0≤x≤1. 
     
     
         9 . The method of  claim 7 , wherein the back barrier layer is located in the GaN layer separated from the first interface by a first thickness of a first portion of the GaN layer. 
     
     
         10 . The method of  claim 9 , wherein the first thickness is in a range of 25 to 350 nanometers. 
     
     
         11 . The method of  claim 7 , wherein a second thickness of the back barrier layer is in a range of 0.5 and 10 nanometers. 
     
     
         12 . The method of  claim 7 , wherein electrons in the 2-DEG in the GaN layer at the first interface is blocked by a second interface between the first portion of the GaN layer and the back barrier layer. 
     
     
         13 . The method of  claim 7 , wherein a third thickness of the GaN layer is in a range of 300 and 1500 nanometers. 
     
     
         14 . A method of making a High Electron Mobility Transistor (HEMT), comprising:
 forming a Gallium Nitride (GaN) layer;   forming a front barrier layer over the GaN layer;   forming a source electrode, a drain electrode, and a gate electrode over the front barrier layer;   providing a gas in the GaN layer at a first interface between the GaN layer and the front barrier layer; and   forming a back barrier layer in the GaN layer.   
     
     
         15 . The method of  claim 14 , wherein the back barrier layer comprises Aluminum Nitride (AlN) and the front barrier layer comprises Aluminum Gallium Nitride (Al x Ga 1-x N), and wherein 0≤x≤1. 
     
     
         16 . The method of  claim 14 , wherein the back barrier layer is located in the GaN layer separated from the first interface by a first thickness of a first portion of the GaN layer. 
     
     
         17 . The method of  claim 16 , wherein the first thickness is in a range of 25 and 350 nanometers. 
     
     
         18 . The method of  claim 14 , wherein a second thickness of the back barrier layer is in a range of 0.5 and 10 nanometers. 
     
     
         19 . The method of  claim 14 , wherein the gas comprises a 2-Dimensional Electron Gas (2-DEG), and wherein electrons in the 2-DEG in the GaN layer at the first interface is blocked by a second interface between the first portion of the GaN layer and the back barrier layer. 
     
     
         20 . The method of  claim 14 , wherein a third thickness of the GaN layer is in a range of 300 and 1500 nanometers.

Join the waitlist — get patent alerts

Track US2022384630A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.