Insulated gate bipolar transistor and diode

Abstract

A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a continuously laid around line-shaped pattern, and a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

1 - 14 . (canceled) 
     
     
         15 . An RC-IGBT (Reverse Conducting—Insulated Gate Bipolar Transistor) semiconductor device comprising:
 a semiconductor layer that has a first main surface on one side and a second main surface on the other side; 
 a gate structure that is arranged at the first main surface; 
 a gate pad that is arranged at the first main surface and that is electrically connected to the gate structure; 
 a collector region of a first conductivity type that is formed in a surface layer portion of the second main surface; 
 a plurality of cathode line regions of a second conductivity type that are formed in the surface layer portion of the second main surface such as not to overlap the gate pad as viewed in plan, that each extends as a band in a first direction X as viewed in plan and that are arranged at an interval in a second direction Y orthogonal to the first direction X; and 
 a pn-junction region that is formed over at least one cathode line region in the semiconductor layer as viewed in cross section and that has a portion overlapping to said one cathode line region as viewed in plan; 
 wherein the cathode line regions each has a first end portion that is located at the gate pad side as viewed in plan and a second end portion that is located at an opposite side to the gate pad, and 
 positions of the second end portions of the cathode line regions in the first direction X are aligned with each other in the second direction Y as viewed in plan. 
 
     
     
         16 . The RC-IGBT semiconductor device according to  claim 15 ,
 wherein the gate structure has a gate trench that is formed in the semiconductor layer, and   the pn-junction region is formed in a region shallower than a bottom portion of the gate trench in a thickness direction of the semiconductor layer.   
     
     
         17 . The RC-IGBT semiconductor device according to  claim 16 ,
 wherein, on the second main surface side, a total planer area of the cathode line regions is smaller than a planer area of a region other than the cathode line regions as viewed in plan.   
     
     
         18 . The RC-IGBT semiconductor device according to  claim 17 , further comprising:
 an insulating layer that is formed on the first main surface and that has a width greater than an opening width of the gate trench.   
     
     
         19 . The RC-IGBT semiconductor device according to  claim 17 ,
 wherein the gate pad is arranged at a peripheral portion of the first main surface as viewed in plan.   
     
     
         20 . The RC-IGBT semiconductor device according to  claim 19 ,
 wherein the gate pad is arranged along a middle portion of one side of the first main surface as viewed in plan.   
     
     
         21 . The RC-IGBT semiconductor device according to  claim 19 ,
 wherein the cathode line regions include at least one cathode line region that does not face the gate pad in the first direction X as viewed in plan and at least one cathode line region that does not face the gate pad in the second direction Y as viewed in plan.   
     
     
         22 . The RC-IGBT semiconductor device according to  claim 21 ,
 wherein the cathode line regions include at least one cathode line region that does not face the gate pad in both of the first direction X and the second direction Y as viewed in plan.   
     
     
         23 . The RC-IGBT semiconductor device according to  claim 19 ,
 wherein, as viewed in plan, the second main surface includes an opposing region that opposes the gate pad, a first region that is located at one side in the second direction Y with respect to the opposing region and a second region that is located at the other side in the second direction Y with respect to the opposing region, and   as viewed in plan, the cathode line regions are formed in the surface layer portion of the second main surface such as not to be located at the opposing region, the first region and the second region.   
     
     
         24 . The RC-IGBT semiconductor device according to  claim 23 ,
 wherein the cathode line regions include at least one cathode line region that faces the first region in the first direction X as viewed in plan and at least one cathode line region that faces the second region in the first direction X as viewed in plan.   
     
     
         25 . The RC-IGBT semiconductor device according to  claim 24 ,
 wherein positions of the first end portions of the cathode line regions in the first direction X are aligned with each other in the second direction Y as viewed in plan.   
     
     
         26 . The RC-IGBT semiconductor device according to  claim 25 ,
 wherein, with respect to the first direction X, the cathode line regions each has a line length greater than a width of the gate pad.   
     
     
         27 . The RC-IGBT semiconductor device according to  claim 26 ,
 wherein, with respect to the second direction Y, the cathode line regions each has a line width smaller than a width of the gate pad.   
     
     
         28 . The RC-IGBT semiconductor device according to  claim 19 ,
 wherein, when a cross line that extends along the first direction X and the second direction Y is set in a central portion of the second main surface such as to divide the second main surface into four regions as viewed in plan, a part of the cathode line regions is included in at least one region of the four regions.   
     
     
         29 . The RC-IGBT semiconductor device according to  claim 15 ,
 wherein, when a line that intersects the gate pad in the first direction X as viewed in plan is set, the cathode line regions are arranged line-symmetrically with respect to said line.   
     
     
         30 . The RC-IGBT semiconductor device according to  claim 16 ,
 wherein the collector region is formed in a whole region of the surface layer portion of the second main surface, and   the cathode line regions are formed such as to replace the first conductive type of the collector region with the second conductive type.   
     
     
         31 . The RC-IGBT semiconductor device according to  claim 15 ,
 wherein the gate structures are formed in a stripe shape as viewed in plan.   
     
     
         32 . The RC-IGBT semiconductor device according to  claim 15 , further comprising:
 a gate finger that is selectively routed at the first main surface, that includes a straight line portion extending in the first direction X as viewed in plan and that is electrically connected to the gate pad;   wherein the cathode line regions extend parallel to the straight line portion of the gate finger as viewed in plan.   
     
     
         33 . The RC-IGBT semiconductor device according to  claim 15 , further comprising:
 a collector electrode that covers the second main surface to be electrically connected to the collector region and the cathode line regions.   
     
     
         34 . The RC-IGBT semiconductor device according to  claim 15 ,
 wherein the gate structure consists of a trench gate structure that includes a trench formed in the first main surface, a gate insulating film covering a wall surface of the trench and a gate electrode embedded in the trench via the gate insulating film.   
     
     
         35 . The RC-IGBT semiconductor device according to  claim 34 ,
 wherein the pn-junction region includes a channel region of the first conductivity type that is formed in a surface layer portion of the first main surface such as to be exposed from the trench, and an emitter region of the second conductivity type that is formed in a surface layer portion of the channel region such as to be exposed from the trench.   
     
     
         36 . The RC-IGBT semiconductor device according to  claim 35 , further comprising:
 a contact recessed portion that is formed in the first main surface at an interval from the gate structure such as to expose the emitter region; and   a contact region of the first conductive type that is formed in a region along the contact recessed portion in the channel region and that has an impurity concentration higher than an impurity concentration of the channel region.   
     
     
         37 . The RC-IGBT semiconductor device according to  claim 35 , further comprising:
 an emitter pad that covers the first main surface at an interval from the gate pad and that is electrically connected to the emitter region;   wherein the cathode line regions are formed in the surface layer portion of the second main surface such as to overlap the emitter pad as viewed in plan.   
     
     
         38 . The RC-IGBT semiconductor device according to  claim 37 , further comprising:
 an insulating layer that is formed on the first main surface;   wherein the gate pad is arranged on the insulating layer, and   the emitter pad is arranged on the insulating layer.