Semiconductor structure, package structure, and manufacturing method thereof

Abstract

A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 at least one integrated circuit component, comprising:
 a first semiconductor substrate; and 
 a second semiconductor substrate, stacked on and electrically coupled to each other, wherein at least one of the first semiconductor substrate and the second semiconductor substrate comprises a first embedded capacitor, and the first embedded capacitor has non-planar three-layer structure. 
   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first semiconductor substrate comprises first hybrid bonding structures disposed on a first side of the first semiconductor substrate, the second semiconductor substrate comprises second hybrid bonding structures disposed on a second side of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are electrically coupled to each other through bonding the first hybrid bonding structures and the second hybrid bonding structures. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the second semiconductor substrate further comprises first through silicon vias penetrating therethrough, wherein the first through silicon vias are free from the first semiconductor substrate and are electrically coupled to the first semiconductor substrate, and the first through silicon vias are arranged aside of a positioning location of the first embedded capacitor comprised in the second semiconductor substrate. 
     
     
         4 . The semiconductor structure of  claim 1 , further comprising:
 a third semiconductor substrate, interposed between and electrically coupled to the first semiconductor substrate and the second semiconductor substrate, wherein the third semiconductor substrate comprises a second embedded capacitor, and the second embedded capacitor has non-planar three-layer structure.   
     
     
         5 . The semiconductor structure of  claim 4 , wherein the third semiconductor substrate further comprises second through silicon vias penetrating therethrough, wherein the second through silicon vias are free from and are electrically coupled to the first semiconductor substrate and the second semiconductor substrate, and the second through silicon vias are arranged aside of a positioning location of the second embedded capacitor comprised in the third semiconductor substrate. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising:
 a third semiconductor substrate, interposed between and electrically coupled to the first semiconductor substrate and the second semiconductor substrate, wherein the third semiconductor substrate comprises a plurality of through vias, and the plurality of through vias are electrically coupled to the first semiconductor substrate and the second semiconductor substrate.   
     
     
         7 . The semiconductor structure of  claim 1 , further comprising:
 a third semiconductor substrate, stacked on and electrically coupled to the first semiconductor substrate and the second semiconductor substrate, the second semiconductor substrate being interposed between the first semiconductor substrate and the third semiconductor substrate, wherein the third semiconductor substrate comprises a second embedded capacitor, and the second embedded capacitor has non-planar three-layer structure.   
     
     
         8 . The semiconductor structure of  claim 7 , wherein the third semiconductor substrate further comprises second through silicon vias penetrating therethrough, wherein the second through silicon vias are free from and are electrically coupled to the first semiconductor substrate and the second semiconductor substrate, and the second through silicon vias are arranged aside of a positioning location of the second embedded capacitor comprised in the third semiconductor substrate. 
     
     
         9 . The semiconductor structure of  claim 1 , further comprising:
 a third semiconductor substrate, stacked on and electrically coupled to the first semiconductor substrate and the second semiconductor substrate, the second semiconductor substrate being interposed between the first semiconductor substrate and the third semiconductor substrate, wherein the third semiconductor substrate comprises a plurality of through vias, and the plurality of through vias are electrically coupled to the first semiconductor substrate and the second semiconductor substrate.   
     
     
         10 . The semiconductor structure of  claim 1 , wherein the first semiconductor substrate further comprises a third embedded capacitor, and the third embedded capacitor has non-planar three-layer structure. 
     
     
         11 . A package structure, comprising:
 at least one integrated circuit component, comprising:
 a first semiconductor substrate; and 
 a second semiconductor substrate having at least one first capacitor embedded therein, electrically coupled to the first semiconductor substrate, wherein the second semiconductor substrate comprises first through silicon vias penetrating therethrough, the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface being free of the first through silicon vias; and 
   an insulating encapsulation, encapsulating the at least one integrated circuit component.   
     
     
         12 . The package structure of  claim 11 , wherein the first semiconductor substrate further comprises first hybrid bonding structures disposed on an active surface of the first semiconductor substrate, the second semiconductor substrate further comprises second hybrid bonding structures disposed on a first side of the second semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate are electrically coupled to each other through bonding the first hybrid bonding structures and the second hybrid bonding structures. 
     
     
         13 . The package structure of  claim 11 , wherein the first through silicon vias are arranged aside of a positioning location of the at least one first capacitor, and the first through silicon vias are electrically coupled to the first semiconductor substrate. 
     
     
         14 . The package structure of  claim 11 , wherein the at least one integrated circuit component further comprises a third semiconductor substrate having at least one second active device or at least one second capacitor embedded therein, and the second semiconductor substrate and the third semiconductor substrate are bonded through a second hybrid bonding interface, wherein the second semiconductor substrate is located between the first semiconductor substrate and the third semiconductor substrate. 
     
     
         15 . The package structure of  claim 14 , wherein the second semiconductor substrate further comprises third hybrid bonding structures disposed on a second side opposite to the first side, the third semiconductor substrate further comprises fourth hybrid bonding structures disposed on an active surface of the third semiconductor substrate, and the second semiconductor substrate and the third semiconductor substrate are electrically coupled to each other through bonding the third hybrid bonding structures and the fourth hybrid bonding structures. 
     
     
         16 . The package structure of  claim 14 , wherein the third semiconductor substrate further comprises second through silicon vias arranged aside of a positioning location of the at least one second active device or the at least one second capacitor, and the second through silicon vias are electrically coupled to the first semiconductor substrate. 
     
     
         17 . The package structure of  claim 14 , further comprising:
 a redistribution structure, located on and electrically coupled to the at least one integrated circuit component;   through pillars, located aside of the at least one integrated circuit component and molded in the insulating encapsulation; and   a plurality of conductive elements, located on the redistribution circuit structure, wherein the the redistribution circuit structure is located between the insulating encapsulation and the plurality of conductive elements.   
     
     
         18 . The package structure of  claim 14 , wherein the at least one second active device comprises a cache device, a memory device, a memory device stack, or combinations thereof. 
     
     
         19 . A package structure, comprising:
 at least one integrated circuit component, comprising:
 a first semiconductor substrate; and 
 a second semiconductor substrate having at least one first capacitor embedded therein, electrically coupled to the first semiconductor substrate, wherein the second semiconductor substrate comprises first through silicon vias penetrating therethrough, the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface being free of the first through silicon vias; 
   an insulating encapsulation, encapsulating the at least one integrated circuit component;   a redistribution structure, located on the insulating encapsulation and electrically coupled to the at least one integrated circuit component; and   a plurality of terminals, located on the redistribution circuit structure, wherein the redistribution circuit structure is located between the insulating encapsulation and the plurality of terminals.   
     
     
         20 . The package structure of  claim 19 , further comprising at least one of:
 a plurality of conductive pillars, next to and electrically coupled to the at least one integrated circuit component, wherein the plurality of conductive pillars penetrate through the insulating encapsulation and are electrically coupled to the redistribution circuit structure; or   at least one passive device, disposed on and electrically coupled to the redistribution structure, wherein the at least one passive device is next to the plurality of conductive elements.