Semiconductor device with power-saving mode and associated methods and systems

Abstract

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may disable ECC functions of the memory devices. When the ECC function is disabled by the host device, the memory device may deactivate various ECC periphery components coupled with an ECC circuit of the memory device to reduce power consumption of the memory device. In some cases, the memory device may disconnect an electrical power supply to the ECC periphery components. In other cases, the memory device may selectively disable the ECC periphery components or block an access command from reaching the ECC periphery components during an access operation. Further, the ECC array may be configured to replace faulty portions of a main array of the memory device when the ECC function is disabled.

What is claimed is: 
     
         1 . An apparatus comprising:
 a memory array including a plurality of memory cells, the memory array including a first portion configured to store user data and a second portion configured to store error checking and correcting (ECC) data associated with the user data;   an ECC circuit that is coupled with the second portion and performs an ECC function for the user data;   a register configured to indicate whether the ECC function is enabled or disabled; and   circuitry configured to:
 determine the ECC function is disabled based on accessing the register; and 
 after determining that the ECC function is disabled, replace a defective segment of the first portion of the memory array with a replacement segment of the second portion of the memory array. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the circuitry is configured to replace the defective segment with the replacement segment by updating address mapping information stored in a nonvolatile memory array of the apparatus. 
     
     
         3 . The apparatus of  claim 2 , wherein the nonvolatile memory array is one of a fuse array or a flash memory array. 
     
     
         4 . The apparatus of  claim 1 , wherein the defective segment and the replacement segment each comprise a single column of the memory array. 
     
     
         5 . The apparatus of  claim 1 , wherein the defective segment and the replacement segment each comprise a plurality of adjacent columns of the memory array. 
     
     
         6 . The apparatus of  claim 1 , further comprising access circuitry configured, in response to an access command identifying the defective segment, to access memory cells of the replacement segment. 
     
     
         7 . A method comprising:
 receiving, at a register of a memory device that comprises the register and a memory array having a first portion configured to store user data and a second portion configured to store error checking and correcting (ECC) data associated with the user data, signaling that indicates an ECC function of the memory device is disabled;   determining that the ECC function of the memory device is disabled based at least in part on a value of the register set by the signaling; and   replacing, based at least in part on determining that the ECC function of the memory device is disabled, a defective segment of the first portion of the memory array with a replacement segment of the second portion of the memory array.   
     
     
         8 . The method of  claim 7 , wherein replacing the defective segment with the replacement segment comprising updating address mapping information stored in a nonvolatile memory array of the memory device. 
     
     
         9 . The method of  claim 8 , wherein the nonvolatile memory array is one of a fuse array or a flash memory array. 
     
     
         10 . The method of  claim 7 , wherein the defective segment and the replacement segment each comprise a single column of the memory array. 
     
     
         11 . The method of  claim 7 , wherein the defective segment and the replacement segment each comprise a plurality of adjacent columns of the memory array. 
     
     
         12 . The method of  claim 7 , further comprising accessing, in response to an access command identifying the defective segment, memory cells of the replacement segment. 
     
     
         13 . A memory system comprising:
 a host device; and   a memory device comprising:
 a memory array that comprises a first portion configured to store user data and a second portion configured to store ECC data associated with the user data; 
 a register configured to indicate whether the ECC function is enabled or disabled based at least in part on signaling received from the host device; and 
 circuitry configured to:
 determine the ECC function is disabled based on accessing the register; and 
 after determining that the ECC function is disabled, replace a defective segment of the first portion of the memory array with a replacement segment of the second portion of the memory array 
 
   
     
     
         14 . The memory system of  claim 13 , wherein the circuitry is configured to replace the defective segment with the replacement segment by updating address mapping information stored in a nonvolatile memory array of the apparatus. 
     
     
         15 . The memory system of  claim 14 , wherein the nonvolatile memory array is one of a fuse array or a flash memory array. 
     
     
         16 . The memory system of  claim 13 , wherein the defective segment and the replacement segment each comprise a single column of the memory array. 
     
     
         17 . The memory system of  claim 13 , wherein the defective segment and the replacement segment each comprise a plurality of adjacent columns of the memory array. 
     
     
         18 . The memory system of  claim 13 , wherein the memory device further comprises access circuitry configured, in response to an access command received from the host that identifies the defective segment, to access memory cells of the replacement segment.