Soic chip architecture

Abstract

A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

What is claimed is: 
     
         1 . A method, comprising:
 forming a redistribution layer on a device die;   encasing the redistribution layer in an encapsulant to form a redistribution circuit structure of the device die;   forming electrical connectors on a first surface of the device die;   connecting the electrical connectors to a second surface of the device die by a through-silicon via (TSV) in the device die to form an interconnection device die; and   arranging a plurality of system on integrated chip (SOIC) device dice on a first surface of the interconnection device die, wherein at least one of the SOIC device dice comprises a memory cell and a processor coupled to the memory cell.   
     
     
         2 . The method of  claim 1 , wherein connecting the electrical connectors to the second surface of the device die comprises forming a connection path between the second surface of the interconnection device die and one or more of the electrical connector and the redistribution circuit structure. 
     
     
         3 . The method of  claim 1 , wherein connecting the electrical connectors to the second surface of the device die comprises forming a channel in the device die to couple the electrical connectors to the second surface of the device die opposite to the first surface of the interconnection device die. 
     
     
         4 . The method of  claim 1 , wherein arranging the plurality of SOIC device dice comprises arranging at least one three dimensional integrated circuit (3DIC) die on the first surface of the interconnection device die. 
     
     
         5 . The method of  claim 1 , wherein arranging the plurality of SOIC device dice comprises arranging the plurality of SOIC device dice on the first surface of the interconnection device die, each of the plurality of SOIC device dice comprising a plurality of memory dice stacked in a face to back (F2B) configuration. 
     
     
         6 . The method of  claim 1 , wherein arranging the plurality of SOIC device dice comprises arranging the plurality of SOIC device dice on the first surface of the interconnection device die, each of the plurality of SOIC device dice comprising a processor, and wherein the processor and the SOIC device die are arranged in a face to face (F2F) configuration with the interconnection device die. 
     
     
         7 . The method of  claim 6 , further comprising coupling the processor to the SOIC device die through the interconnection device die. 
     
     
         8 . A method, comprising:
 forming an interconnection device die comprising a redistribution circuit structure and a plurality of electrical connectors coupled by a through-silicon via (TSV);   arranging a plurality of device dice on the interconnection device die; and   coupling the device dice to the interconnection device die via the electrical connectors.   
     
     
         9 . The method of  claim 8 , further comprising insulating the redistribution circuit structure by embedding conductors therein in an encapsulant. 
     
     
         10 . The method of  claim 8 , further comprising connecting the conductors to conductive terminals arranged on a first surface of the interconnection device die. 
     
     
         11 . The method of  claim 8 , further comprising bonding an electrical connector of a three dimensional integrated circuit (3DIC) of the plurality of device dice to a corresponding one of the plurality of electrical connectors of the interconnection device die. 
     
     
         12 . The method of  claim 8 , further comprising arranging at least one the device die and the interconnection device die in a F2F configuration. 
     
     
         13 . The method of  claim 8 , further comprising connecting the TSV between at least one of the device die at a first surface of the interconnection device die and a second surface of the interconnection device die. 
     
     
         14 . The method of  claim 8 , wherein a pitch between adjacent electrical connectors in the plurality of electrical connectors is less than or equal to about 9 μm. 
     
     
         15 . The method of  claim 8 , wherein a width of each electrical connector of the plurality of electrical connectors is between about 2 μm and about 30 μm. 
     
     
         16 . The method of  claim 8 , wherein the plurality of electrical connectors comprise one or more of ball-type electrical connectors, bump electrical connectors, metal pad electrical connectors, and combinations thereof. 
     
     
         17 . The method of  claim 8 , wherein a 3DIC of the plurality of device dice comprises a plurality of memory dice stacked in a face to back (F2B) configuration. 
     
     
         18 . A method, comprising:
 forming a logic die;   forming a plurality of memory dies;   forming a through-silicon via (TSV) in one or more of the plurality of memory dies;   stacking the logic die and one or more of the plurality of memory dies on top of one another;   aligning system on integrated chip (SOIC) structures using alignment marks as a guide; and   bonding contact surfaces of the stacked dies to one another.   
     
     
         19 . The method of  claim 18 , further comprising connecting an active region of a first one of the plurality of memory dies through electrical connectors to a metallization layer on a back surface of a second one of the plurality of memory dies. 
     
     
         20 . The method of  claim 18 , wherein bonding contact surfaces of the stacked dies comprises bonding the contact surfaces of the stacked dies using one or more of hybrid bonding, fusion bonding, anodic bonding, direct bonding, room temperature bonding, pressure bonding, and combinations thereof.