Power saving circuit for embedded battery applications

Abstract

A battery-disconnect circuit may include a latch, a battery-disconnect subcircuit, and a power-enable subcircuit. The battery-disconnect subcircuit may be configured to control current leakage. The battery-disconnect subcircuit may be connected to the latch. The latch may be configured to maintain a power supply state of the battery-disconnect subcircuit, a no-power supply state of the battery-disconnect subcircuit, or both. The power-enable subcircuit may be connected to the battery-disconnect subcircuit. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the power supply state based on an enable signal. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the no-power supply state based on an off signal.

What is claimed is: 
     
         1 . A battery-disconnect circuit comprising:
 a latch;   a battery-disconnect subcircuit configured to control current leakage and connected to the latch, the latch configured to maintain a power supply state and a no-power supply state of the battery-disconnect subcircuit; and   a power-enable subcircuit connected to the battery-disconnect subcircuit, wherein an enable signal switches the battery-disconnect subcircuit to the power supply state and an off signal switches the battery-disconnect subcircuit to the no-power supply state.   
     
     
         2 . The battery-disconnect circuit of  claim 1 , wherein the battery-disconnect subcircuit comprises a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET). 
     
     
         3 . The battery-disconnect circuit of  claim 2 , wherein the latch is a NOR S/R latch that comprises an input terminal and a Vcc terminal, wherein the input terminal is connected to the gate of the PMOS FET and the Vcc terminal is connected to the source of the PMOS FET. 
     
     
         4 . The battery-disconnect circuit of  claim 2 , wherein the latch is a microcontroller that comprises an IO terminal and a Vcc terminal, wherein the IO terminal is connected to the gate of the PMOS FET and the Vcc terminal is connected to the source of the PMOS FET. 
     
     
         5 . The battery-disconnect circuit of  claim 1  further comprising:
 a level shifting buffer that comprises a p-type metal-oxide semiconductor field-effect transistor (PMOS FET) and a first n-type metal-oxide semiconductor field-effect transistor (NMOS FET) and a second NMOS FET. 
 
     
     
         6 . The battery-disconnect circuit of  claim 5 , wherein a gate of the first NMOS FET and a gate of the second NMOS FET are connected to a drain of the PMOS FET. 
     
     
         7 . The battery-disconnect circuit of  claim 5 , wherein the latch comprises a first inverter and a second inverter, wherein an input terminal of the first inverter is connected to a capacitor and an output terminal of the first inverter is connected to an input terminal of the second inverter, and an output terminal of the second inverter is connected to a gate terminal of the battery-disconnect subcircuit. 
     
     
         8 . The battery-disconnect circuit of  claim 1  further comprising:
 a signal level shifting inverter configured to control signals to the latch. 
 
     
     
         9 . The battery-disconnect circuit of  claim 8 , wherein the signal level shifting inverter is configured to set the latch and switch the battery-disconnect subcircuit to the power supply state in response to the on signal. 
     
     
         10 . The battery-disconnect circuit of  claim 8 , wherein the signal level shifting inverter is configured to clear the latch and switch the battery-disconnect subcircuit to the no-power supply state in response to the off signal. 
     
     
         11 . An image capture device comprising:
 a battery;   a processor; and   a battery-disconnect circuit connected to the battery and the processor, the battery-disconnect circuit comprising:
 a latch; 
 a battery-disconnect subcircuit configured to control current leakage and connected to the latch, the latch configured to maintain a power supply state and a no-power supply state of the battery-disconnect subcircuit; and 
 a power-enable subcircuit connected to the battery-disconnect subcircuit, wherein an enable signal switches the battery-disconnect subcircuit to the power supply state and an off signal switches the battery-disconnect subcircuit to the no-power supply state. 
   
     
     
         12 . The image capture device of  claim 11 , wherein the battery-disconnect subcircuit comprises a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET). 
     
     
         13 . The image capture device of  claim 12 , wherein the latch is a NOR S/R latch that comprises an input terminal and a Vcc terminal, wherein the input terminal is connected to the gate of the PMOS FET and the Vcc terminal is connected to the source of the PMOS FET. 
     
     
         14 . The image capture device of  claim 12 , wherein the latch is a microcontroller that comprises an TO terminal and a Vcc terminal, wherein the TO terminal is connected to the gate of the PMOS FET and the Vcc terminal is connected to the source of the PMOS FET. 
     
     
         15 . The image capture device of  claim 11 , wherein the battery-disconnect subcircuit further comprises:
 a level shifting buffer that comprises a p-type metal-oxide semiconductor field-effect transistor (PMOS FET) and a first n-type metal-oxide semiconductor field-effect transistor (NMOS FET) and a second NMOS FET.   
     
     
         16 . The image capture device of  claim 15 , wherein a gate of the first NMOS FET and a gate terminal of the second NMOS FET are connected to a drain terminal of the PMOS FET. 
     
     
         17 . The image capture device of  claim 15 , wherein the latch comprises a first inverter and a second inverter, wherein an input terminal of the first inverter is connected to a capacitor and an output terminal of the first inverter is connected to an input terminal of the second inverter, wherein an output terminal of the second inverter is connected to a gate terminal of the battery-disconnect subcircuit. 
     
     
         18 . The image capture device of  claim 11 , wherein the battery-disconnect circuit further comprises:
 a signal level shifting inverter configured to control signals to the latch, wherein the signal level shifting inverter is configured to set the latch and switch the battery-disconnect subcircuit to the power supply state in response to the on signal.   
     
     
         19 . The image capture device of  claim 11 , wherein the battery-disconnect circuit further comprises:
 a signal level shifting inverter configured to control signals to the latch, wherein the signal level shifting inverter is configured to clear the latch and switch the battery-disconnect subcircuit to the no-power supply state in response to the off signal.   
     
     
         20 . A battery-disconnect circuit comprising:
 a latch;   a battery-disconnect subcircuit connected to the latch, the latch configured to maintain a power supply state and a no-power supply state of the battery-disconnect subcircuit;   a power-enable subcircuit connected to the battery-disconnect subcircuit, wherein an enable signal switches the battery-disconnect subcircuit to the power supply state; and   an on-off subcircuit connected to the battery-disconnect subcircuit, wherein an on signal switches the battery-disconnect subcircuit to the power supply state and an off signal switches the battery-disconnect subcircuit to the no-power supply state, wherein the on-off subcircuit is configured to control current leakage.