US2022368122A1PendingUtilityA1

Driver assisted esd protection apparatus and method

Assignee: INTEL CORPPriority: Jun 11, 2020Filed: Jul 28, 2022Published: Nov 17, 2022
Est. expiryJun 11, 2040(~13.9 yrs left)· nominal 20-yr term from priority
H02H 9/046H02H 3/08
69
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) TO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus, comprising:
 a pad;   a driver coupled to the pad, wherein the driver comprises a pull up device coupled in a series path with a pull down device, the pull up device is coupled to a power supply rail, the pull down device is coupled to ground and the pad is coupled to a point in the series path, the point is between the pull up device and the pull down device;   a timer circuit coupled to the pad via the power supply rail, wherein the timer circuit is to output a signal indicating whether an Electro Static Discharge (ESD) event occurs on the pad;   a first logic gate having an output coupled to a gate of the pull up device; and   a second logic gate having an output coupled to a gate of the pull down device, wherein the first logic gate has a first input coupled to the timer circuit, the second logic gate has a first input coupled to the timer circuit, and the second logic gate is to turn on the pull down device during the ESD event to ground the pad via the pull down device.   
     
     
         2 . The apparatus of  claim 1 , wherein the first logic gate has a second input coupled to an input data path. 
     
     
         3 . The apparatus of  claim 1 , wherein the second logic gate has a second input coupled to an input data path. 
     
     
         4 . The apparatus of  claim 1 , wherein the pull down device comprises an n-type device. 
     
     
         5 . The apparatus of  claim 1 , wherein the pull up device comprises a p-type device. 
     
     
         6 . The apparatus of  claim 1 , wherein the second logic gate is to turn off the pull down device when the ESD event completes. 
     
     
         7 . The apparatus of  claim 1 , wherein the first input of the first logic gate is coupled to the timer circuit via an inverter, to receive an inverse of the signal. 
     
     
         8 . The apparatus of  claim 1 , wherein the first input of the second logic gate receives the signal. 
     
     
         9 . The apparatus of  claim 1 , wherein the signal is low during the ESD event. 
     
     
         10 . The apparatus of  claim 1 , wherein the first logic gate is to control the pull up device during the ESD event. 
     
     
         11 . The apparatus of  claim 1 , wherein the first logic gate comprises a NOR gate and the second logic gate comprises a NAND gate. 
     
     
         12 . The apparatus of  claim 1 , further comprising a clamp circuit to turn on for a duration of the ESD event in response to the signal, to provide a path from the power supply rail to ground. 
     
     
         13 . The apparatus of  claim 1 , wherein the timer circuit comprises a resistor-capacitor path coupled to a buffer. 
     
     
         14 . An apparatus, comprising:
 a pull up device coupled in a series path with a pull down device, wherein the pull up device is coupled to a power supply rail, the pull down device is coupled to ground and a pad is coupled to a point in the series path, the point is between the pull up device and the pull down device;   a circuit coupled to the pad via the power supply rail, wherein the circuit is to output a signal indicating whether an Electro Static Discharge (ESD) event occurs on the pad; and   a logic gate having an output coupled to a gate of the pull down device, wherein the logic gate having the output coupled to the gate of the pull down device is responsive to the signal to turn on the pull down device during the ESD event to ground the pad via the pull down device.   
     
     
         15 . The apparatus of  claim 14 , further comprising:
 a logic gate having an output coupled to a gate of the pull up device, wherein the logic gate having the output coupled to the gate of the pull up device is responsive to the signal to control the pull up device during the ESD event.   
     
     
         16 . The apparatus of  claim 14 , wherein the circuit is coupled to the pad via the power supply rail and a diode. 
     
     
         17 . The apparatus of  claim 14 , wherein the circuit is to set the signal to indicate a duration of the ESD event. 
     
     
         18 . An apparatus, comprising:
 a pull down device coupled at one side to ground and at another side to a pad;   a circuit coupled to the pad via a power supply rail, wherein the circuit is to output a signal indicating whether an Electro Static Discharge (ESD) event occurs on the pad; and   a logic gate having an output coupled to a gate of the pull down device, wherein the logic gate having the output coupled to the gate of the pull down device is responsive to the signal to turn on the pull down device during the ESD event to ground the pad via the pull down device.   
     
     
         19 . The apparatus of  claim 18 , wherein the logic gate comprises a NAND gate. 
     
     
         20 . The apparatus of  claim 18 , further comprising:
 a pull up device coupled to the pull down device, wherein the pull up device is coupled at one side to the power supply rail and at another side to the pad and the pull down device; and   a logic gate having an output coupled to a gate of the pull up device, wherein the logic gate having the output coupled to the gate of the pull up device is responsive to the signal to control the pull up device during the ESD event.

Join the waitlist — get patent alerts

Track US2022368122A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.