Structure and Method for Single Gate Non-Volatile Memory Device

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a silicide-containing field effect transistor disposed in a periphery region and a floating gate non-volatile memory device disposed in a memory region. The floating gate non-volatile memory device is free of silicide. The floating gate non-volatile memory device includes a second source, a third source, a fourth source, a second drain, and a third drain. The floating gate non-volatile memory device also includes a first floating gate electrode associated with the second source, the second drain, and the third source, and a second floating gate electrode associated with the second source, the third drain, and the fourth source. The second source is disposed between the first and second floating gate electrodes with a constant width. Each of the third source and the fourth source has a width larger than the constant width of the second source.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a field effect transistor disposed in a periphery region of a substrate, the field effect transistor including a gate electrode, a first source, a first drain, wherein a silicide feature is disposed on the first source and the first drain; and   a floating gate non-volatile memory device disposed in a memory region of the substrate, wherein the floating gate non-volatile memory device is free of any silicide feature, and the floating gate non-volatile memory device includes:
 a second source, a third source, a fourth source, a second drain, and a third drain disposed along an axis in an order of the third source, the second drain, the second source, the third drain, and the fourth source; 
 a first floating gate electrode associated with the second source, the second drain, and the third source in the memory region; and 
 a second floating gate electrode associated with the second source, the third drain, and the fourth source in the memory region, the second floating gate electrode being physically spaced apart from the first floating gate electrode along the axis, wherein the second source is disposed between the first floating gate electrode and the second floating gate electrode with a constant width an entire length between the first floating gate electrode and the second floating gate electrode, the constant width measured in a direction perpendicular to the axis, and wherein each of the third source and the fourth source has a width measured in the direction perpendicular to the axis which is larger than the constant width of the second source. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the substrate includes a first type of dopant in the periphery region, and wherein the first source and the first drain include a second type of dopant that is different from the first type of dopant. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the substrate includes a first type of dopant in the memory region, and wherein the second source, the third source, the fourth source, the second drain, and the third drain include a second type of dopant that is different from the first type of dopant. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the floating gate non-volatile memory device further includes a hard mask layer disposed on the second source, the third source, the fourth source, the second drain, and the third drain, and wherein the periphery region is substantially free of the hard mask layer. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the periphery region includes an etch stop layer in physical contact with the silicide feature, and wherein in the memory region the etch stop layer is spaced apart from the second source, the third source, the fourth source, the second drain, and the third drain by the hard mask layer. 
     
     
         6 . The semiconductor device of  claim 1 , wherein each of the first floating gate electrode and the second floating gate electrode includes a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion and the third portion extend lengthwise in the direction perpendicular to the axis, and wherein the second portion is disposed between the first portion and the third portion and extends lengthwise along the axis. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the first portion has a first width measured along the axis, the second portion has a second width measured along the axis, and wherein the first width is different from the second width. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the floating gate non-volatile memory device further includes two and only two contacts disposed on each of the second drain and the third drain. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the floating gate non-volatile memory device further includes one and only one contact disposed on each of the second source, the third source, and the fourth source. 
     
     
         10 . The semiconductor device of  claim 1 , wherein each of the second drain and the third drain extends lengthwise in the direction perpendicular to the axis. 
     
     
         11 . A semiconductor device comprising:
 a field effect transistor disposed in a periphery region of a substrate, the field effect transistor including a gate electrode, a first source, a first drain, wherein the field effect transistor includes silicide; and   a floating gate memory device disposed in a memory region of the substrate, the floating gate memory device including a second source, a second drain, a third source, a third drain, a fourth source, a first floating gate electrode associated with the second source, the second drain, and the third source, and a second floating gate electrode associated with the second source, the third drain, and the fourth source,
 wherein the second floating gate electrode is physically spaced apart from the first floating gate electrode, 
 wherein the second source is disposed lengthwise between the first floating gate electrode and the second floating gate electrode, wherein the second source has a constant width an entire length between the first floating gate electrode and the second floating gate electrode, wherein each of the third source and the fourth source has a width that is larger than the constant width of the second source, and 
 wherein the floating gate memory device is free of silicide. 
   
     
     
         12 . The semiconductor device of  claim 11 , further comprising:
 a first contact disposed directly on the second source;   an injection bit line coupled to the first contact;   a second contact disposed directly on the third source; and   a read bit line coupled to the second contact.   
     
     
         13 . The semiconductor device of  claim 12 , further comprising:
 a third contact and a fourth contact disposed directly on the second drain; and   a word line coupled to the third contact and the fourth contact.   
     
     
         14 . The semiconductor device of  claim 11 , wherein the first floating gate electrode includes at least a first portion, a second portion, and a third portion, the first portion disposed between the second source and the second drain, the second portion disposed between the third source and the second drain, and the third portion disposed over the second drain and configured to physically connect the first portion to the second portion. 
     
     
         15 . The semiconductor device of  claim 14 , wherein a width of the first portion is smaller than a width of the second portion. 
     
     
         16 . The semiconductor device of  claim 11 , wherein the silicide is disposed on the first source and the first drain of the field effect transistor. 
     
     
         17 . An integrated circuit, comprising:
 a semiconductor substrate having a periphery region and a memory region, wherein the semiconductor substrate has a top surface;   a field effect transistor disposed in the periphery region, the field effect transistor including a gate electrode, a first source, and a first drain; and   a memory device disposed in the memory region, the memory device including a floating gate electrode, a second source, a third source, and a second drain,
 wherein: 
 the second drain is disposed between the second source and the third source, 
 the floating gate electrode includes a first portion, a second portion, and a third portion, 
 the second portion is disposed between the first portion and the third portion, 
 the second portion includes a first side surface and a second side surface opposite the first side surface, 
 each of the first side surface and the second side surface is disposed directly above the second drain, 
 the second drain comprises a heavily doped drain feature that includes a bottom surface, and 
 the bottom surface is away from the top surface of the semiconductor substrate at a constant distance from a plane of the first side surface to a plane of the second side surface. 
   
     
     
         18 . The integrated circuit of  claim 17 , wherein the field effect transistor further includes a first gate dielectric layer under the gate electrode, the memory device further includes a second gate dielectric layer under the floating gate electrode, and the first gate dielectric layer and the second gate dielectric layer have different thicknesses. 
     
     
         19 . The integrated circuit of  claim 17 , wherein the field effect transistor further includes silicide, and wherein the memory device is substantially free of silicide. 
     
     
         20 . The integrated circuit of  claim 17 , wherein the semiconductor substrate includes a first type of dopant in the memory region, and wherein the second source, the third source, and the second drain include a second type of dopant that is different from the first type of dopant.