Hardened interlayer dielectric layer

Abstract

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

What is claimed is: 
     
         1 . A device, comprising:
 a substrate;   a first interlayer dielectric (ILD) layer over the substrate, wherein the first ILD layer comprises a first dielectric having a dielectric constant less than about 3.3 and a hardness of at least about 3 GPa; and   an interconnect formed in the first ILD layer, the interconnect having a pitch less than about 40 nm.   
     
     
         2 . The device of  claim 1 , wherein a refractive index of the first ILD layer is at least about 1.42 for light having a wavelength of 633 nm. 
     
     
         3 . The device of  claim 1 , wherein a density of the first ILD is at least about 1.6 g/cm 3 . 
     
     
         4 . The device of  claim 1  wherein the first ILD layer comprises a porous, carbon-doped material. 
     
     
         5 . The device of  claim 1 , further comprising a second ILD layer above the first ILD layer. 
     
     
         6 . The device of  claim 5 , further comprising an etch stop layer between the first ILD layer and the second ILD layer. 
     
     
         7 . The device of  claim 5 , wherein:
 the second ILD layer has a dielectric constant substantially equal to that of the first ILD layer; and   the second ILD layer has a hardness substantially equal to that of the first ILD layer.   
     
     
         8 . The device of  claim 5 , wherein:
 the second ILD layer has a dielectric constant different from that of the first ILD layer; and   the second ILD layer has a hardness different from that of the first ILD layer.   
     
     
         9 . The device of  claim 1 , wherein the dielectric constant of the first ILD layer is about 3.0 and the hardness of the first ILD layer is about 5 GPa. 
     
     
         10 . The device of  claim 1 , wherein a critical dimension (CD) bias of the interconnect formed in the first ILD layer is less about 3 nm. 
     
     
         11 . A semiconductor device, comprising:
 a semiconductor substrate;   a first interlayer dielectric (ILD) layer on the substrate, the first ILD layer having a hardness of at least about 3.2 GPa;   vias and metal lines in the first ILD layer, the vias having a via pitch and the metal lines having a metal line pitch; and   a second ILD layer over the first ILD layer, the second ILD layer having interconnects with an interconnect pitch that greater than the via pitch and the metal line pitch.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the hardness of the first ILD layer is between about 3.2 GPa and about 7 GPa. 
     
     
         13 . The semiconductor device of  claim 11 , wherein a dielectric constant of the first ILD layer is between about 2.9 and about 3.2. 
     
     
         14 . The semiconductor device of  claim 11 , wherein a refractive index of the first ILD layer is between about 1.42 and about 1.48. 
     
     
         15 . The semiconductor device of  claim 11 , wherein a density of the first ILD layer is between about 1.6 g/cm 3  and about 1.9 g/cm 3 . 
     
     
         16 . The semiconductor device of  claim 11 , wherein the interconnect pitch is between about 28 nm and about 39 nm. 
     
     
         17 . A device, comprising:
 a substrate;   a porous carbon-doped interlayer dielectric (ILD) layer above the substrate, the porous carbon-doped ILD layer having a hardness greater than about 3 GPa;   a first plurality of interconnects formed in the porous carbon-doped ILD layer, the first plurality of interconnects having a first pitch less than about 40 nm;   a second ILD layer above the first plurality of interconnects; and   a second plurality of interconnects formed in the second ILD layer, the second plurality of interconnects having a second pitch greater than the first pitch.   
     
     
         18 . The device of  claim 17 , wherein the substrate comprises transistors in electrical contact with the first and second pluralities of interconnects. 
     
     
         19 . The device of  claim 17 , wherein the substrate comprises an etch stop layer under the porous carbon-doped ILD layer. 
     
     
         20 . The device of  claim 19 , wherein the first plurality of interconnects comprise vias that extend through the etch stop layer and, adjacent to the vias, metal lines that do not extend through the etch stop layer.