Event handling in pipeline execute stages

Abstract

A method includes receiving an execute packet that includes a first instruction and a second instruction and executing the first instruction and the second instruction using a pipeline. Executing the first and second instructions includes storing a result of the first instruction in a holding register; determining whether an event that interrupts execution of the execute packet occurs prior to completion of the executing of the second instruction; and based on the event not occurring, committing the result of the first instruction after completion of the executing of the second instruction.

1 . A method comprising:
 receiving a packet that includes a first instruction and a second instruction;   beginning execution of the first instruction by a processor execution pipeline;   beginning execution of the second instruction by the processor execution pipeline, wherein execution of the first instruction completes during execution of the second instruction;   based on the execution of the first instruction completing during execution of the second instruction, storing a result of the first instruction in a holding register; and   based on the execution of the second instruction completing, committing the result of the first instruction.   
     
     
         2 . The method of  claim 1 , wherein the committing of the result of the first instruction includes copying the first instruction from the holding register to a destination register file. 
     
     
         3 . The method of  claim 1  further comprising determining whether an interrupt occurred during the execution of the first instruction or the execution of the second instruction. 
     
     
         4 . The method of  claim 3  further comprising, based on the interrupt:
 flushing the result of the first instruction from the holding register; 
 restarting execution of the first instruction; 
 restarting execution of the second instruction; and 
 re-storing the result of the first instruction in the holding register, wherein the committing the result of the first instruction is performed after the re-storing the result of the first instruction in the holding register. 
 
     
     
         5 . The method of  claim 1  further comprising:
 detecting a fault associated with the second instruction; and 
 based on the fault:
 flushing the result of the first instruction from the holding register; 
 restarting execution of the first instruction; 
 restarting execution of the second instruction; and 
 re-storing the result of the first instruction in the holding register, wherein the committing the result of the first instruction is performed after the re-storing the result of the first instruction in the holding register. 
 
 
     
     
         6 . The method of  claim 5 , wherein the fault includes at least one of: a page fault, a write conflict, a divide-by-zero error, an error in a cache return data status, or a matrix multiplication error. 
     
     
         7 . The method of  claim 1  further comprising:
 detecting an event associated with the second instruction; and 
 based on the event continuing to store the result of the first instruction in the holding register until the event completes, wherein the committing the result of the first instruction is performed after the event completes. 
 
     
     
         8 . The method of  claim 7 , wherein the event includes a stall associated with the second instruction. 
     
     
         9 . The method of  claim 1 , wherein the result of the first instruction is provided by an intermediate stage of the processor execution pipeline. 
     
     
         10 . The method of  claim 1 , wherein:
 the result of the first instruction is provided by a first execution stage of the processor execution pipeline; and   a result of the second instruction is provided by a second execution stage of the processor execution pipeline that is subsequent to the first execution stage.   
     
     
         11 . The method of  claim 10 , wherein the first execution stage is an execute one (E1) stage and the second execution stage is an execute two (E2) stage. 
     
     
         12 . The method of  claim 1 , wherein the first instruction is a one-cycle instruction and the second instruction is a two-cycle instruction. 
     
     
         13 . A device comprising:
 a pipeline controller that includes a set of execution stages and a holding register, wherein the pipeline controller is configured to:
 receive a packet that includes a first instruction and a second instruction; 
 cause the set of execution stages to begin execution of the first instruction; 
 cause the set of execution stages to begin execution of the second instruction, wherein execution of the first instruction completes during execution of the second instruction; 
 based on the execution of the first instruction completing during execution of the second instruction, cause the set of execution stages to store a result of the first instruction in the holding register; and 
 based on the execution of the second instruction completing, commit the result of the first instruction. 
   
     
     
         14 . The device of  claim 13 , wherein the committing of the result of the first instruction includes copying the first instruction from the holding register to a destination register file. 
     
     
         15 . The device of  claim 13  further comprising an event controller coupled to the pipeline controller and configured to determine whether an interrupt occurred during the execution of the first instruction or the execution of the second instruction. 
     
     
         16 . The device of  claim 15 , wherein the pipeline controller is configured to, based on the interrupt:
 flush the result of the first instruction from the holding register;   cause the set of execution stages to restart execution of the first instruction;   cause the set of execution stages to restart execution of the second instruction; and   cause the set of execution stages to re-store the result of the first instruction in the holding register.   
     
     
         17 . The device of  claim 13  further comprising an event controller coupled to the pipeline controller and configured to detect a fault associated with the second instruction, wherein the pipeline controller is configured to, based on the fault:
 flush the result of the first instruction from the holding register; 
 cause the set of execution stages to restart execution of the first instruction; 
 cause the set of execution stages to restart execution of the second instruction; and 
 cause the set of execution stages to re-store the result of the first instruction in the holding register. 
 
     
     
         18 . The device of  claim 13 , wherein:
 the set of execution stages includes a first execution stage and a second execution stage that is subsequent to the first execution stages;   the first execution stage is configured to provide the result of the first instruction; and   the second execution stage is configured to provide a result of the second instruction.   
     
     
         19 . The device of  claim 18 , wherein the first execution stage is an execute one (E1) stage and the second execution stage is an execute two (E2) stage. 
     
     
         20 . The device of  claim 13 , wherein the first instruction is a one-cycle instruction and the second instruction is a two-cycle instruction.