Matrix processing instruction with optional up/down sampling of matrix

Abstract

A processor system comprises a shared memory and a processing element. The processing element includes a matrix processor unit and is in communication with the shared memory. The processing element is configured to receive a processor instruction specifying a data matrix and a matrix manipulation operation. A manipulation matrix based on the processor instruction is identified. The data matrix and the manipulation matrix are used to perform a matrix operation to determine a result matrix.

What is claimed is: 
     
         1 . A system, comprising:
 a memory; and   a processing element in communication with the memory, wherein the processing element is configured to:
 receive a processor instruction specifying a data matrix and a matrix manipulation operation, wherein the processing element is configured with a capability to selectively perform a plurality of different types of matrix manipulation operation options, the plurality of different types of matrix manipulation operation options including a matrix dimension up-sampling type operation option and a matrix dimension down-sampling type operation option, and the matrix manipulation operation specified by the received processor instruction is one of the plurality of different types of matrix manipulation operation options; 
 automatically select from a repository of predefined manipulation matrices, a manipulation matrix based on the matrix manipulation operation specified in the processor instruction; and 
 perform a matrix operation using the data matrix and the selected manipulation matrix to determine a result matrix. 
   
     
     
         2 . The system of  claim 1 , wherein the data matrix is retrieved from the memory. 
     
     
         3 . The system of  claim 1 , wherein the selected manipulation matrix is retrieved from a local memory of the processing element. 
     
     
         4 . The system of  claim 1 , wherein the matrix operation performed is a matrix multiplication operation. 
     
     
         5 . The system of  claim 1 , wherein the result matrix is stored on a storage on the processing element. 
     
     
         6 . The system of  claim 1 , wherein the processing element is one of a plurality of processing elements configured to operate in parallel. 
     
     
         7 . The system of  claim 1 , wherein the result matrix is outputted using an output unit included in the system. 
     
     
         8 . The system of  claim 7 , wherein the output unit is configured to perform multiple duplicative writes to output an up-sampled result matrix. 
     
     
         9 . The system of  claim 1 , wherein the selected manipulation matrix is an up-sampling matrix. 
     
     
         10 . The system of  claim 9 , wherein the up-sampling matrix is configured to perform a linear interpolation between row elements. 
     
     
         11 . The system of  claim 1 , wherein the selected manipulation matrix is a down-sampling matrix. 
     
     
         12 . The system of  claim 1 , wherein the processing element includes:
 a first type of register configured to store values of a single row of the data matrix;   a group of a second type of registers, wherein each of the second type of registers is configured to store values of a different column of the selected manipulation matrix; and   a plurality of vector calculation units, wherein each of the plurality of vector calculation units corresponds to one of the second type of registers, and each of the vector calculation units is configured to multiply each value stored in the first type of register with a corresponding value stored in the corresponding one of the second type of registers and sum together multiplication results of the corresponding vector calculation unit to at least in part determine a corresponding element in the result matrix of multiplying the data matrix with the selected manipulation matrix.   
     
     
         13 . The system of  claim 12 , wherein the first type of register is configured to broadcast contents to each of the plurality of vector calculation units. 
     
     
         14 . The system of  claim 12 , wherein each of the plurality of vector calculation units includes a vector multiply unit and a vector adder unit. 
     
     
         15 . A method, comprising:
 receiving at a processing element a processor instruction specifying a data matrix and a matrix manipulation operation, wherein processing element is configured with a capability to selectively perform a plurality of different types of matrix manipulation operation options, the plurality of different types of matrix manipulation operation options including a matrix dimension up-sampling type operation option and a matrix dimension down-sampling type operation option, and the matrix manipulation operation specified by the received processor instruction is one of the plurality of different types of matrix manipulation operation options;   automatically selecting from a repository of predefined manipulation matrices, a manipulation matrix based on the matrix manipulation operation specified in the processor instruction; and   performing a matrix operation using the data matrix and the selected manipulation matrix to determine a result matrix.   
     
     
         16 . The method of  claim 15 , wherein performing the matrix operation includes:
 loading each one of a column of the selected manipulation matrix into one of a plurality of vector calculation units; and   broadcasting a row of the data matrix to each of the plurality of vector calculation units.   
     
     
         17 . The method of  claim 16 , wherein performing the matrix operation includes:
 for each of the plurality of vector calculation units:
 multiplying elements of the broadcasted row of the data matrix with corresponding elements of the corresponding loaded column of the selected manipulation matrix to determine multiplication results; and 
 summing together the multiplication results of the corresponding vector calculation unit to determine a corresponding element of a corresponding row of the result matrix of multiplying the data matrix with the selected manipulation matrix. 
   
     
     
         18 . A system, comprising:
 a memory; and   a plurality of processing elements configured to operate in parallel, wherein at least one processing element of the plurality of processing elements is configured to configured to:
 receive a processor instruction specifying a data matrix and a matrix manipulation operation, wherein the processing element is configured with a capability to selectively perform a plurality of different types of matrix manipulation operation options, the plurality of different types of matrix manipulation operation options including a matrix dimension up-sampling type operation option and a matrix dimension down-sampling type operation option, and the matrix manipulation operation specified by the received processor instruction is one of the plurality of different types of matrix manipulation operation options; 
 automatically select from a repository of predefined manipulation matrices, a manipulation matrix based on the matrix manipulation operation specified in the processor instruction; and 
 perform a matrix operation using the data matrix and the selected manipulation matrix to determine a result matrix. 
   
     
     
         19 . The system of  claim 18 , wherein the selected manipulation matrix is an up-sampling matrix. 
     
     
         20 . The system of  claim 18 , wherein the at least one processing element includes:
 a first type of register configured to store values of a single row of the data matrix;   a group of a second type of registers, wherein each of the second type of registers is configured to store values of a different column of the selected manipulation matrix; and   a plurality of vector calculation units, wherein each of the plurality of vector calculation units corresponds to one of the second type of registers, and each of the vector calculation units is configured to multiply each value stored in the first type of register with a corresponding value stored in the corresponding one of the second type of registers and sum together multiplication results of the corresponding vector calculation unit to at least in part determine a corresponding element in the result matrix of multiplying the data matrix with the selected manipulation matrix.