US2022365705A1PendingUtilityA1

Object management in tiered memory systems

Assignee: MICRON TECHNOLOGY INCPriority: May 17, 2021Filed: May 17, 2021Published: Nov 17, 2022
Est. expiryMay 17, 2041(~14.8 yrs left)· nominal 20-yr term from priority
Inventors:Reshmi Basu
G06F 3/061G06F 3/068G06F 3/0679G06F 3/065G06F 3/0604G06F 3/0655G06F 12/1081G06F 12/0893G06F 12/1009G06F 12/0646G06F 12/0638
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Claims

Abstract

Systems, apparatuses, and methods related to object management in tiered memory systems are discussed. An example method can include writing data representative of a memory object of a first memory device. The first memory device can include a first type of memory medium includes a NAND Flash or a NOR Flash. The example method can include determining that a data size of the memory object is less than a threshold data size. The method can include writing the data representative of the memory object to a second memory device that includes a second type of memory medium. The second memory medium is a non-volatile memory that includes phase-change memory or resistive random access memory.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method, comprising:
 writing data representative of a memory object to a first memory device that comprises a first type of memory medium;   determining that a size of the memory object is less than a threshold data size; and   writing the data representative of the memory object to a second memory device that comprises a second type of memory medium different than the first type;   wherein the first type of memory medium comprises NAND Flash or NOR Flash and the second type of memory medium is a non-volatile memory medium comprising phase-change memory or resistive random access memory (RAM).   
     
     
         2 . The method of  claim 1 , wherein an address space of the first memory device and the second memory device is contiguous across both the first memory device and the second memory device. 
     
     
         3 . The method of  claim 1 , wherein writing the data representative of the memory object comprises initially writing the data representative of the memory object to the non-volatile memory medium. 
     
     
         4 . The method of  claim 3 , wherein writing the data representative of the memory object comprises writing the data representative of the memory object to the second memory medium in response to the size of the particular one memory object being less than a page size associated with the first memory medium. 
     
     
         5 . The method of  claim 4 , wherein the page size is a NAND page. 
     
     
         6 . The method of  claim 4 , wherein the page size is around 16 kilobytes (KBs). 
     
     
         7 . The method of  claim 1 , wherein:
 the data representative of the memory object is written to the second memory medium in response to a request from a host to receive access to the memory object.   
     
     
         8 . The method of  claim 1 , wherein the threshold data size is a data size of a flash-based memory page. 
     
     
         9 . A system, comprising:
 a first memory device that comprises a first type of memory medium, the first type of memory medium comprising NAND Flash or NOR Flash;   a second memory device that comprises a second type of memory medium, the second memory medium is a non-volatile memory comprising phase-change memory or resistive random access memory (RAM); and   a controller coupled to the first memory device and the second memory device, the controller configured to:
 write data representative of a plurality of memory objects to the first memory device; 
 receive a request to access data representative of a memory object of the plurality of memory objects in the first memory device; 
 determine whether a size of the data of the memory object of the plurality of memory objects is less than a threshold data size; and 
 in response to the size of the data representative of the memory object being less than the threshold data size, writing the data representative of the memory object associated with the data to the second memory device. 
   
     
     
         10 . The system of  claim 9 , wherein an address space to store data representative of each of the plurality of memory objects contiguously spans across the second memory device and the first memory device. 
     
     
         11 . The system of  claim 9 , wherein the controller is further configured to, in response to the size of the data of a different memory object being equal to or greater than the threshold data size, read the data representative of the different memory object associated with the data from the first memory device. 
     
     
         12 . The system of  claim 9 , wherein, in response to the data representative of the memory object associated with the data being written to the second memory device, the controller is configured to access a portion of the data representative of the memory object including the data in the second memory device. 
     
     
         13 . The system of  claim 11 , wherein the controller is configured to not access a portion of the data representative of the memory object in the second memory device that does not include the data. 
     
     
         14 . The system of  claim 9 , further comprising a host, wherein the host is configured to send a request for the data stored in the first memory device to the controller. 
     
     
         15 . The system of  claim 14 , wherein the host is further configured to, in response to the particular memory object associated with the data being written to the second device, receive the data via the controller from the second memory device. 
     
     
         16 . The system of  claim 9 , wherein neither the first memory device nor the second memory device is used as a cache in the memory system. 
     
     
         17 . The system of  claim 9 , further comprising a host, wherein the host is configured to enable data representative of a memory object of the plurality of memory objects to be sent:
 to the first memory device using a double-data rate (DDR) protocol; and   to the second memory device using a flash-based memory express (NVME) protocol.   
     
     
         18 . A system, comprising
 a first memory device comprising a first type of memory medium;   a second memory device comprising a second type of memory medium; and   a controller coupled to the first memory device and the second memory device and configured to:
 write data representative of each of a plurality of memory objects to the first memory device; and 
 in response to a size of data representative of a particular one of the plurality of memory objects being less than a page size of the first memory device, writing the data representative of the particular one memory object to the second memory device; 
   wherein:   the first type of memory medium comprises NAND Flash or NOR Flash;   the second type of memory medium is a non-volatile memory comprising phase-change memory or resistive random access memory (RAM); and   an address space associated with the first memory device and the second memory device contiguously spans across both the first memory device and the second memory device.   
     
     
         19 . The system of  claim 18 , wherein the page size is a NAND page size. 
     
     
         20 . The system of  claim 18 , wherein the controller is configured to write the data representative of the plurality of memory objects to the second memory device using a key value database structure.

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