Analog to digital converter and a method for analog to digital conversion

Abstract

An analog to digital converter (ADC) that may include an input configured to receive a first signal and a second signal; a signal generator that is configured to generate multiple signals, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream; wherein the first sampled stream and the second sampled stream are generated based on at least one of the phase shifted clock signals; and a processing unit that is configured to receive at least some of the multiple signals, the at least some of the multiple signals may include the first PWM related signals, the second PWM related signals, and the phase related signals; generate, based on the at least some of the multiple samples, virtual counter values and virtual phase values that are mutually aligned; determine a value of a difference between the first signal and the second signal, and output an ADC output signal indicative of the difference between the first signal and the second signal.

We claim: 
     
         1 . An analog to digital converter (ADC) comprising:
 an input configured to receive a first signal and a second signal;   a signal generator that is configured to generate multiple signals, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream; wherein the first sampled stream and the second sampled stream are generated based on at least one of the phase shifted clock signals;   a processing unit that is configured to: receive at least some of the multiple signals, the at least some of the multiple signals may include the first PWM related signals, the second PWM related signals, and the phase related signals; generate, based on the at least some of the multiple samples, virtual counter values and virtual phase values that are mutually aligned; determine a value of a difference between the first signal and the second signal, and output an ADC output signal indicative of the difference between the first signal and the second signal.   
     
     
         2 . The ADC according to  claim 1  wherein the processing unit is configured to determine a value of the difference by applying a linear operation. 
     
     
         3 . The ADC according to  claim 1  wherein the signal generator may include a counter that is configured to be fed by a clock-associated phase-shifted clock signal of the multiple phase-shifted clock signals, and to output a counter output. 
     
     
         4 . The ADC according to  claim 3  wherein the signal generator further may include one or more samplers that are configured to convert the counter output to the first sampled stream and the second sampled stream. 
     
     
         5 . The ADC according to  claim 4  wherein the signal generator may include one or more encoders for generating a first phase change signal and a second phase change signal that are indicative of a predefined phase change in each one of the first sampled stream and the second sampled stream, respectively; wherein the first phase change signal and the second phase change signal belong to the phase related signals. 
     
     
         6 . The ADC according to  claim 5  wherein the signal generator may include a first sampling latch (SL) that is configured to (a) receive a first PWM pulse, the first PWM pulse is indicative of the first signal, (b) receive the phase-shifted clock signals that are phase shifted from each other, (c) output a first end signal indicative of a value of the first sampled counter output at an end of the first PWM pulse, (d) output a second end signal indicative of a value of the second sampled counter output at the end of the first PWM pulse; and (e) output a third end signal indicative of values of the phase-shifted clock signals at the end of the first PWM pulse; wherein the first end signal, the second end signal and the third end signal belong to the first PWM related signals. 
     
     
         7 . The ADC according to  claim 6  wherein the signal generator may include a second SL that is configured to (a) receive a second PWM pulse, the second PWM pulse is indicative of the second signal, (b) receive the phase-shifted clock signals that are phase shifted from each other, (c) output a fourth end signal indicative of a value of the first sampled counter output at an end of the second PWM pulse, (d) output a fifth end signal indicative of a value of the second sampled counter output at the end of the second PWM pulse, and (e) output a sixth end signal indicative of values of the phase-shifted clock signals at the end of the second PWM pulse; wherein the fourth end signal, the fifth end signal and the sixth end signal belong to the second PWM related signals. 
     
     
         8 . The ADC according to  claim 1  wherein the processing circuit is configured to generate a first phase state signal and a second phase state signal, calculate first virtual phase value based on the first phase state signal, and calculate a second virtual phase value based on the second phase state signal. 
     
     
         9 . The ADC according to  claim 8  wherein the processing circuit is configured to determine the value of the difference based on the first virtual phase value and on the second virtual phase value. 
     
     
         10 . The ADC according to  claim 8  wherein the processing circuit is configured to select between the first end signal to the second end signal to provide a first selected end signal;
 select between the third end signal to the fourth end signal to provide a second selected end signal; 
 determine a first virtual counter value based on the first selected end signal; and determine a second virtual counter value based on the second selected end signal. 
 
     
     
         11 . A method for analog to digital conversion, the method may include:
 receiving, by an input, a first signal and a second signal;   generating multiple signals by a signal generator, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream;   wherein the first sampled stream and the second sampled stream are generated based on at least one of the phase shifted clock signals;   receiving, by a processing unit, at least some of the multiple signals, the at least some of the multiple signals may include the first PWM related signals, the second PWM related signals, and the phase related signals;   generating, based on the at least some of the multiple samples, virtual counter values and virtual phase values that are mutually aligned;   determining a value of a difference between the first signal and the second signal, and outputting an ADC output signal indicative of the difference between the first signal and the second signal.   
     
     
         12 . The method according to  claim 11  comprising determining a value of the difference by applying a linear operation. 
     
     
         13 . The method according to  claim 11  wherein the signal generator may include a counter, wherein the method may include receiving by the counter a clock-associated phase-shifted clock signal of the multiple phase-shifted clock signals, and to outputting by the counter a counter output. 
     
     
         14 . The method according to  claim 13  wherein the signal generator further may include one or more samplers wherein the method may include converting, by the one or more samplers, the counter output to the first sampled stream and the second sampled stream. 
     
     
         15 . The method according to  claim 14  wherein the signal generator may include one or more encoders, wherein the method may include generating, by the one or more encoders, a first phase change signal and a second phase change signal that are indicative of a predefined phase change in each one of the first sampled stream and the second sampled stream, respectively; wherein the first phase change signal and the second phase change signal belong to the phase related signals. 
     
     
         16 . The method according to  claim 15  wherein the signal generator may include a first sampling latch (SL), wherein the method may include (a) receiving, by the first SL, a first PWM pulse, the first PWM pulse is indicative of the first signal, (b) receiving, by the first SL, the phase-shifted clock signals that are phase shifted from each other, (c) outputting, by the first SL, a first end signal indicative of a value of the first sampled counter output at an end of the first PWM pulse, (d) outputting, by the first SL, a second end signal indicative of a value of the second sampled counter output at the end of the first PWM pulse; and (e) outputting, by the first SL, a third end signal indicative of values of the phase-shifted clock signals at the end of the first PWM pulse; wherein the first end signal, the second end signal and the third end signal belong to the first PWM related signals. 
     
     
         17 . The method according to  claim 16  wherein the signal generator may include a second SL, wherein the method may include (a) receiving, by the second SL, a second PWM pulse, the second PWM pulse is indicative of the second signal, (b) receiving, by the second SL, the phase-shifted clock signals that are phase shifted from each other, (c) outputting, by the second SL, a fourth end signal indicative of a value of the first sampled counter output at an end of the second PWM pulse, (d) outputting, by the second SL, a fifth end signal indicative of a value of the second sampled counter output at the end of the second PWM pulse, and (e) outputting, by the second SL, a sixth end signal indicative of values of the phase-shifted clock signals at the end of the second PWM pulse; wherein the fourth end signal, the fifth end signal and the sixth end signal belong to the second PWM related signals. 
     
     
         18 . The method according to  claim 11  wherein comprising generating, by the processing circuit, a first phase state signal and a second phase state signal, calculating first virtual phase value based on the first phase state signal, and calculating a second virtual phase value based on the second phase state signal. 
     
     
         19 . The method according to  claim 18  comprising determining, by the processing circuit, the value of the difference based on the first virtual phase value and on the second virtual phase value. 
     
     
         20 . The method according to  claim 18  comprising selecting, by the processing circuit, between the first end signal to the second end signal to provide a first selected end signal;
 selecting between the third end signal to the fourth end signal to provide a second selected end signal; determining a first virtual counter value based on the first selected end signal; and 
 determining a second virtual counter value based on the second selected end signal.