Gate structure for semiconductor device

Abstract

The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.

What is claimed is: 
     
         1 . A method, comprising:
 forming a gate structure over a substrate;   removing a first portion of the gate structure to form a first recess;   forming a first dielectric layer over the first recess, comprising:
 forming a first portion of the first dielectric layer over a lower portion of side surfaces of the first recess; and 
 forming a second portion of the first dielectric layer over an upper portion of the side surfaces of the first recess; and 
   forming a gate electrode over the first portion of the first dielectric layer while exposing the second portion of the first dielectric layer, wherein a top surface of the gate electrode is below a top of the first recess.   
     
     
         2 . The method of  claim 1 , wherein the forming the gate electrode over the first portion of the first dielectric layer while exposing the second portion of the first dielectric layer comprises:
 forming a gate metal stack over the first recess; and   selectively removing a portion of the gate metal stack, formed over the second portion of the first dielectric layer, from the first dielectric layer.   
     
     
         3 . The method of  claim 1 , wherein the forming the second portion of the first dielectric layer over the upper portion of the side surfaces of the first recess comprises:
 forming a dielectric structure to surround the gate structure; and   forming the second portion of the first dielectric layer over the top of the first recess and over sides of the dielectric structure.   
     
     
         4 . The method of  claim 1 , further comprising:
 forming a second dielectric layer to surround the gate structure;   removing a second portion of the gate structure to form a second recess to expose a portion of side surfaces of the second dielectric layer, wherein the exposed portion of the side surfaces of the second dielectric layer is positioned above the upper portion of the side surfaces of the first recess; and   forming the first dielectric layer over the portion of side surfaces of the second dielectric layer.   
     
     
         5 . A method, comprising
 forming, on a semiconductor substrate, vertical structures having therein source/drain regions and a channel region comprising one or more doped semiconductor materials;   forming isolation structures between the vertical structures;   forming a sacrificial gate structure overlying channel regions of the vertical structures;   recessing the sacrificial gate structure;   forming opposing gate spacers adjacent to the sacrificial gate structure;   replacing the sacrificial gate structure with a metal gate structure, comprising:
 forming a gate dielectric layer; and 
 forming a metal gate structure, wherein the gate dielectric layer and the opposing gate spacers extend above a top surface of the metal gate structure; 
   depositing a contact etch stop layer (CESL) over the vertical structures and the isolation structures;   depositing an inter-layer dielectric (ILD) over the etch stop layer; and   forming contacts to the source/drain regions through the ILD.   
     
     
         6 . The method of  claim 5 , wherein forming the metal gate structure further comprises forming a padding layer between the metal gate structure and the ILD. 
     
     
         7 . The method of  claim 5 , wherein forming the metal gate structure comprises forming the metal gate structure over a plurality of stacked channels. 
     
     
         8 . The method of  claim 7 , wherein forming the metal gate structure over a plurality of stacked channels comprises epitaxially growing a plurality of channel layers. 
     
     
         9 . The method of  claim 5 , wherein depositing the CESL comprises lining sidewalk of the contacts with the CESL. 
     
     
         10 . The method of  claim 5 , wherein forming gate dielectric layer comprises extending the gate dielectric layer over top surfaces of the opposing spacers. 
     
     
         11 . A method, comprising:
 forming a first vertical structure over a substrate, the first vertical structure comprising a channel region;   forming a second vertical structure over the substrate, the second vertical structure comprising a dielectric stack; and   forming a gate structure over channel regions of the first and second vertical structures, wherein forming the gate structure comprises:
 forming two opposing spacers over the channel region of the first vertical structure; 
 forming a first dielectric layer over side surfaces of the two opposing spacers, the first dielectric layer comprising two opposing side surfaces and top surfaces positioned above the two opposing side surfaces of the first dielectric layer; and 
 forming a gate metal stack between the two opposing side surfaces of the first dielectric layer, wherein a top surface of the gate metal stack is below the top surfaces of the first dielectric layer. 
   
     
     
         12 . The method of  claim 11 , wherein forming the gate metal stack comprises forming the top surface of the gate metal stack below a top surface of the second vertical structure. 
     
     
         13 . The method of  claim 11 , wherein forming the two opposing spacers comprises forming top surfaces of the two opposing spacers above or substantially coplanar with a top surface of the second vertical structure. 
     
     
         14 . The method of  claim 11 , wherein forming the first dielectric layer comprises disposing the first dielectric layer over top surfaces of the two opposing spacers. 
     
     
         15 . The method of  claim 11 , wherein forming the dielectric stack of the second vertical structure comprises forming a second dielectric layer and a third dielectric layer disposed over the second dielectric layer, wherein the second dielectric layer comprises a low-k dielectric material and the third dielectric layer comprises hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO x ), hafnium silicon oxide (FfSiO x ), or a high-k dielectric material. 
     
     
         16 . The method of  claim 11 , wherein forming the first dielectric layer comprises forming a layer of one or more of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (AL 2 O 3 ), hafnium aluminum oxide (HfAlO x ), hafnium silicon oxide (HfSiO x ), and combinations thereof. 
     
     
         17 . The method of  claim 11 , wherein forming the channel region of the first vertical structure comprises forming alternating layers of silicon and silicon-germanium. 
     
     
         18 . The method of  claim 11 , wherein forming the gate structure comprises surrounding a top surface and side surfaces of a portion of the first vertical structure with the gate structure. 
     
     
         19 . The method of  claim 11 , wherein forming the first vertical structure comprises disposing a top surface of the first vertical structure below a top surface of the second vertical structure. 
     
     
         20 . The method of  claim 11 , further comprising forming a contact etch stop layer on the first and second vertical structures.