US2022359701A1PendingUtilityA1

Method for forming semiconductor device structure with hard mask layer over fin structure

Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Aug 22, 2019Filed: Jul 26, 2022Published: Nov 10, 2022
Est. expiryAug 22, 2039(~13.1 yrs left)· nominal 20-yr term from priority
H10P 50/691H10P 50/692B82Y 10/00H01L 21/308H01L 29/6653H01L 29/42392H01L 29/66545H01L 29/7853H01L 29/6681H01L 29/66553H01L 29/0653H10D 64/018H10D 64/017H10D 64/015H10D 62/116H10D 30/6212H10D 30/0243H10D 30/6757H10D 30/43H10D 30/014H10D 30/6735H10D 62/85H10D 62/364H10D 62/151H10D 62/121H10D 62/10H10D 84/834H10D 30/62
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Claims

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a hard mask layer formed over the fin structure. The semiconductor device structure also includes a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer. The semiconductor device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for forming a semiconductor device structure, comprising:
 forming a fin structure over a substrate, wherein the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternating manner;   forming a protection layer over a topmost layer of the plurality of first semiconductor layers;   forming a dummy gate structure over the protection layer;   forming gate spacers over sidewalls of the dummy gate structure;   removing the dummy gate structure and the plurality of first semiconductor layers to form a trench; and   forming a metal gate structure in the trench, wherein the protection layer is surrounded by the metal gate structure.   
     
     
         2 . The method for forming the semiconductor device structure as claimed in  claim 1 , wherein the protection layer is partially etched during the step of forming the trench, and wherein the protection layer has a first portion covered by the gate spacers and a second portion covered by the metal gate structure after the metal gate structure is formed, a first height of the first portion is greater than a second height of the second portion. 
     
     
         3 . The method for forming the semiconductor device structure as claimed in  claim 2 , wherein a ratio of the second height to the first height is greater than or equal to about 0.1 and less than 1. 
     
     
         4 . The method for forming the semiconductor device structure as claimed in  claim 1 , further comprising:
 laterally etching the plurality of first semiconductor layers before the dummy gate structure is removed; and   forming inner spacers over sidewalls of remaining portions of the plurality of first semiconductor layers after the lateral etching.   
     
     
         5 . The method for forming the semiconductor device structure as claimed in  claim 1 , wherein the step of forming the gate spacers further comprises:
 forming a gate spacer layer over the sidewalls of the dummy gate structure and covering a top surface of the protection layer; and   partially removing the gate spacer layer such that the gate spacers are formed.   
     
     
         6 . The method for forming the semiconductor device structure as claimed in  claim 1 , wherein a sidewall of the protection layer is in direct contact with the gate spacers. 
     
     
         7 . The method for forming the semiconductor device structure as claimed in  claim 1 , wherein the step of forming the gate spacers further comprises:
 forming a gate spacer layer over sidewalls of the dummy gate structure, wherein the gate spacer layer is in direct contact with the topmost layer of the plurality of first semiconductor layers; and   partially removing the gate spacer layer such that the gate spacers are formed.   
     
     
         8 . The method for forming the semiconductor device structure as claimed in  claim 1 , wherein forming the metal gate structure comprises:
 forming a high-k dielectric layer between one of the second semiconductor layers and the protection layer.   
     
     
         9 . The method for forming the semiconductor device structure as claimed in  claim 1 , wherein the protection layer has a reversed T-shaped structure. 
     
     
         10 . A method for forming a semiconductor device structure, comprising:
 forming a fin structure over a substrate, wherein the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternating manner;   forming a hard mask layer over the fin structure;   etching a portion of the first semiconductor layers to form an opening;   forming an inner spacer in the trench, wherein the hard mask layer is in direct contact with the inner spacer; and   forming a gate structure over the fin structure, wherein a portion of the gate structure is directly below the hard mask layer.   
     
     
         11 . The method for forming the semiconductor device structure as claimed in  claim 10 , further comprising:
 forming a dummy gate structure over the fin structure; and   forming a gate spacer adjacent to the dummy gate structure, wherein the gate spacer is in direct contact with the hard mask layer.   
     
     
         12 . The method for forming the semiconductor device structure as claimed in  claim 10 , further comprising:
 forming a contact etch stop layer adjacent to the gate structure, wherein the contact etch stop layer is in direct contact with the hard mask layer.   
     
     
         13 . The method for forming the semiconductor device structure as claimed in  claim 10 , further comprising:
 removing a portion of the hard mask layer; and   forming a gate spacer over the hard mask layer.   
     
     
         14 . The method for forming the semiconductor device structure as claimed in  claim 13 , wherein the hard mask layer has a first portion directly below the gate structure and a second portion directly below the gate spacer, and a thickness of the first portion is greater than a thickness of the second portion. 
     
     
         15 . The method for forming the semiconductor device structure as claimed in  claim 10 , wherein forming the gate structure over the fin structure comprises:
 forming a high-k dielectric layer between one of the second semiconductor layers and the hard mask layer.   
     
     
         16 . The method for forming the semiconductor device structure as claimed in  claim 10 , wherein the hard mask layer has a reversed T-shaped structure. 
     
     
         17 . A method for forming a semiconductor device structure, comprising:
 forming a fin structure over a substrate, wherein the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternating manner;   forming a hard mask layer over the fin structure;   forming a dummy gate structure over the hard mask layer;   removing a portion of the hard mask layer outside of the dummy gate structure;   forming a gate spacer adjacent to the hard mask layer;   removing the dummy gate structure and the plurality of first semiconductor layers to form a trench; and   forming a gate structure in the trench, wherein the protection layer is surrounded by the gate structure.   
     
     
         18 . The method for forming the semiconductor device structure as claimed in  claim 17 , wherein a bottom surface of the gate spacer layer is lower than a top surface of the hard mask layer. 
     
     
         19 . The method for forming the semiconductor device structure as claimed in  claim 17 , further comprising:
 forming a contact etch stop layer adjacent to the gate structure, wherein the contact etch stop layer is in direct contact with the hard mask layer.   
     
     
         20 . The method for forming the semiconductor device structure as claimed in  claim 17 , wherein a sidewall surface of the hard mask layer is covered by the gate spacer.

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