Semiconductor Device and Method

Abstract

A semiconductor device including source/drain contacts extending into source/drain regions, below topmost surfaces of the source/drain regions, and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region; a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate;   a first channel region over the semiconductor substrate;   a first gate stack over the semiconductor substrate and surrounding four sides of the first channel region;   a first epitaxial source/drain region adjacent the first gate stack and the first channel region; and   a first source/drain contact coupled to the first epitaxial source/drain region, a bottommost surface of the first source/drain contact extending below a topmost surface of the first channel region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the bottommost surface of the first source/drain contact extends below the topmost surface of the first channel region by greater than 15 nm. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising a second channel region below the first channel region, wherein the bottommost surface of the first source/drain contact extends below a topmost surface of the second channel region. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first source/drain contact extends through a first interlayer dielectric, wherein a spacer separates the first source/drain contact from the first interlayer dielectric. 
     
     
         5 . The semiconductor device of  claim 4 , wherein a topmost surface of the first epitaxial source/drain region is from 10 nm to 20 nm above the bottommost surface of the first source/drain contact. 
     
     
         6 . The semiconductor device of  claim 1 , wherein a bottommost surface of the first gate stack extends below the bottommost surface of the first source/drain contact. 
     
     
         7 . A method comprising:
 forming a gate stack over a semiconductor substrate;   epitaxially growing a first source/drain region in the semiconductor substrate adjacent the gate stack, the epitaxially growing the first source/drain region comprising:
 epitaxially growing a first semiconductor material; 
 epitaxially growing a second semiconductor material over the first semiconductor material; and 
 epitaxially growing a third semiconductor material over the second semiconductor material, wherein an atomic concentration of a dopant in the first semiconductor material is between an atomic concentration of a dopant in the third semiconductor material and an atomic concentration of a dopant in the second semiconductor material; 
   etching the first source/drain region to form a first recess in the first source/drain region, wherein the first recess extends through the third semiconductor material and partially through the second semiconductor material, a bottommost surface of the first recess being disposed above a bottommost surface of the second semiconductor material, wherein etching the first source/drain region comprises iteratively etching the first source/drain region using a first etching process and a second etching process having different etchants from the first etching process; and   forming a first source/drain contact in the first recess and coupled to the first source/drain region.   
     
     
         8 . The method of  claim 7 , wherein etching the first source/drain region with the first etching process comprises generating a first plasma from fluoromethane (CH 3 F) and hydrogen (H 2 ). 
     
     
         9 . The method of  claim 8 , wherein etching the first source/drain region with the second etching process comprises generating a second plasma from nitrogen (N 2 ) and hydrogen (H 2 ). 
     
     
         10 . The method of  claim 7 , wherein the first etching process and the second etching process are repeated for 5 to 20 iterations. 
     
     
         11 . The method of  claim 7 , wherein the first etching process etches the first source/drain region and forms a polymer byproduct along surfaces of the first source/drain region, wherein the second etching process etches the polymer byproduct. 
     
     
         12 . The method of  claim 7 , further comprising:
 forming an interlayer dielectric over the gate stack and the first source/drain region; and   etching the interlayer dielectric to form a second recess exposing the first source/drain region before etching the first source/drain region to form the first recess.   
     
     
         13 . The method of  claim 7 , wherein the first recess has straight sidewalls, wherein a distance between opposite sidewalls of the first recess decreases from a top of the first recess to the bottommost surface of the first recess. 
     
     
         14 . A method comprising:
 forming a multi-layer stack on a semiconductor substrate, the multi-layer stack comprising a first semiconductor layer on the semiconductor substrate and a second semiconductor layer on the first semiconductor layer;   replacing the first semiconductor layer with a gate structure;   forming a source/drain region in the semiconductor substrate adjacent the gate structure;   etching the source/drain region to form a first recess extending to level with a bottom surface of the second semiconductor layer; and   forming a source/drain contact in the first recess.   
     
     
         15 . The method of  claim 14 , further comprising:
 forming a dielectric layer on the gate structure and the source/drain region; and   etching the dielectric layer to form a second recess exposing a top surface of the source/drain region, wherein the source/drain contact is formed in the second recess.   
     
     
         16 . The method of  claim 15 , further comprising forming a first spacer in the second recess lining the dielectric layer, wherein the source/drain contact is formed in contact with the first spacer and the source/drain region. 
     
     
         17 . The method of  claim 16 , wherein a side surface of the first spacer is continuous with a side surface of the source/drain region adjacent the first recess. 
     
     
         18 . The method of  claim 14 , wherein the source/drain region is etched by an iterative etch process including a first etch process and a second etch process, wherein the first etch process deposits a polymer byproduct adjacent the source/drain region, and wherein the second etch process removes the polymer byproduct adjacent the source/drain region. 
     
     
         19 . The method of  claim 14 , wherein the first recess extends to a depth greater than 15 nm from a top surface of the multi-layer stack. 
     
     
         20 . The method of  claim 14 , wherein the first semiconductor layer is formed in physical contact with the semiconductor substrate, wherein the second semiconductor layer is formed in physical contact with the first semiconductor layer, and wherein a distance from the source/drain contact to the second semiconductor layer is less than 6 nm.