Source/Drain Via Having Reduced Resistance

Abstract

A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.

What is claimed is: 
     
         1 . A method, comprising:
 forming a first interlayer dielectric (ILD) over a source/drain;   etching a first opening through the first ILD, wherein the first opening partially exposes the source/drain;   filling the first opening with a source/drain contact;   forming one or more dielectric layers over the first ILD and over the source/drain contact;   etching a second opening through the one or more dielectric layers, wherein the second opening exposes the source/drain contact; and   filling the second opening with a source/drain via, wherein the filling the second opening is performed using a selective metal growth process.   
     
     
         2 . The method of  claim 1 , wherein the filling the second opening is performed without using a glue layer. 
     
     
         3 . The method of  claim 1 , wherein the selective metal growth process includes a selective chemical vapor deposition (CVD). 
     
     
         4 . The method of  claim 3 , wherein the selective CVD is performed at a pressure in a range between about 1 Torr and about 50 Torr, and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius. 
     
     
         5 . The method of  claim 3 , wherein the selective CVD is performed using WF 6  or WCl 5  as a precursor gas. 
     
     
         6 . The method of  claim 5 , wherein the selective CVD is performed by mixing the precursor gas with H 2 . 
     
     
         7 . The method of  claim 1 , wherein the selective metal growth process selectively deposits polycrystalline tungsten on an upper surface of the source/drain contact. 
     
     
         8 . The method of  claim 1 , wherein the forming the one or more dielectric layers includes:
 forming an etching-stop layer over the first ILD and over the source/drain contact; and   forming a second ILD over the etching-stop layer.   
     
     
         9 . The method of  claim 8 , wherein the etching the second opening includes:
 etching a first portion of the second opening in the second ILD; and   etching a second portion of the second opening in the etching-stop layer, wherein the second portion of the second opening is etched to be wider than the first portion of the second opening.   
     
     
         10 . The method of  claim 1 , wherein the first ILD is formed over a gate, and wherein the method further comprises:
 etching a third opening through the one or more dielectric layers and through the first ILD, wherein the third opening partially exposes the gate;   partially filling the third opening with a glue layer; and   completely filling the third opening with a gate via, wherein the gate via is formed on the glue layer.   
     
     
         11 . A method, comprising:
 forming a first interlayer dielectric (ILD) over a source/drain;   performing a first etching process that etches a source/drain contact hole through the first ILD, wherein the first source/drain contact hole partially exposes the source/drain;   depositing a source/drain contact in the first source/drain contact hole;   forming an etching-stop layer over the first ILD and over the source/drain contact;   forming a second ILD over the etching-stop layer;   performing a second etching process that etches a top portion of a source/drain via hole in the etching-stop layer;   performing a third etching process that etches a bottom portion of the source/drain via hole in the second ILD, wherein the bottom portion is etched to be wider than the top portion; and   depositing a source/drain via that fills both the top portion and the bottom portion of the source/drain via hole.   
     
     
         12 . The method of  claim 11 , wherein the depositing the source/drain via is performed without using a glue layer, such that the source/drain via comes into direct contact with an upper surface of the source/drain contact, with side surfaces of the etching-stop layer, and with side surfaces of the second ILD. 
     
     
         13 . The method of  claim 11 , wherein the first ILD is formed over a gate, and wherein the method further comprises:
 etching a gate via hole through the second ILD, through the etching-stop layer, and through the first ILD, wherein the gate via hole partially exposes the gate;   depositing a glue layer on bottom and side surfaces of the gate via hole; and   depositing a gate via on the glue layer, wherein the gate via completely fills the gate via hole.   
     
     
         14 . The method of  claim 11 , wherein the depositing the source/drain via is performed using a selective metal growth process in which polycrystalline tungsten is deposited as the source/drain via, and wherein the selective metal growth process is performed at a pressure in a range between about 1 Torr and about 50 Torr, and at a temperature in a range between about 200 degrees Celsius and about 400 degrees Celsius. 
     
     
         15 . A method, comprising:
 forming a source/drain and a gate structure over a substrate;   forming a first interlayer dielectric (ILD) over the source/drain and over the gate structure;   forming a source/drain contact over the source/drain, wherein the source/drain contact extends through the first ILD vertically;   forming an etching-stop layer over the first ILD;   forming a second ILD over the etching-stop layer;   etching the second ILD and the etching-stop layer to form a first via-hole that exposes the source/drain contact;   forming a source/drain via in the first via-hole, wherein the source/drain via is formed to be in direct physical contact with the source/drain contact, the etching-stop layer, and the second ILD;   after the forming of the source/drain via, etching the second ILD, the etching-stop layer, and the first ILD to form a second via-hole that exposes the gate structure; and   forming a gate via in the second via-hole.   
     
     
         16 . The method of  claim 15 , wherein the etching the second ILD and the etching-stop layer is performed using one or more etching processes in which the etching-stop layer is etched at a greater etching rate than the second ILD. 
     
     
         17 . The method of  claim 15 , further comprising: after the second via-hole has been formed but before the gate via is formed, forming a glue layer on side surfaces of the second via-hole and over the gate structure, wherein the gate via is formed over the glue layer. 
     
     
         18 . The method of  claim 15 , further comprising: after the forming the source/drain via, performing one or more semiconductor fabrication processes using one or more chemicals that have corrosive properties, wherein a material composition of the source/drain via is more resistant to the one or more chemicals than a material composition of the source/drain contact. 
     
     
         19 . The method of  claim 15 , wherein the forming the source/drain via is performed using a selective metal growth process. 
     
     
         20 . The method of  claim 15 , wherein the first via-hole and the second via-hole are formed to be offset from each other in both a first lateral direction and a second lateral direction that is perpendicular to the first lateral direction.