Power device including metal layer

Abstract

A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.

1 .- 21 . (canceled) 
     
     
         22 . A power semiconductor device, comprising:
 a substrate having an edge;   an insulating layer disposed over the substrate;   a metal layer disposed over the insulating layer and including a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness;   a coating layer disposed over the metal layer and having a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the edge of the substrate and the second portion of the metal layer; and   a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer.   
     
     
         23 . The power semiconductor device of  claim 22 , wherein the first thickness of the first portion is in a range from 20% to 60% of the second thickness of the second portion. 
     
     
         24 . The power semiconductor device of  claim 22 , wherein the first thickness of the first portion is in a range from 1 μm to 2 μm, and the second thickness of the second portion is at least 2 μm. 
     
     
         25 . The power semiconductor device of  claim 22 , wherein the first thickness is a distance between an upper surface of the first portion and a lower surface of the first portion at an outer edge of the first portion, and the second thickness is a distance between an upper surface of the second portion and a lower surface of the second portion at an outer edge of the second portion. 
     
     
         26 . The power semiconductor device of  claim 22 , wherein the first portion and the second portion form a single integrated body. 
     
     
         27 . The power semiconductor device of  claim 22 , wherein a distance between an outer edge of the first portion and an outer edge of the second portion is equal to or greater than 20 μm. 
     
     
         28 . The power semiconductor device of  claim 22 , wherein the first portion is spaced apart from the second portion by a distance in a range from 4 μm to 8 μm. 
     
     
         29 . The power semiconductor device of  claim 22 , wherein the metal layer includes Al, Cu, and W. 
     
     
         30 . The power semiconductor device of  claim 22 , wherein the third thickness of the coating layer is greater than 9 μm. 
     
     
         31 . The power semiconductor device of  claim 22 , wherein the coating layer includes a plurality of portions, an adjacent pair of the plurality of portions being spaced apart by a distance in a range from 20 μm to 40 μm. 
     
     
         32 . The power semiconductor device of  claim 22 , wherein the coating layer has a honeycomb structure. 
     
     
         33 . The power semiconductor device of  claim 22 , wherein the third thickness of the coating layer is at least 2 times greater than the second thickness of the second portion. 
     
     
         34 . The power semiconductor device of  claim 22 , wherein the protective layer has a coefficient of thermal expansion (CTE) in a range from 3.4*10 −6 /° C. to 8.0*10 −6 /° C., and the substrate has a CTE in a range from 4.2*10 −6 /° C. to 4.4*10 −6 /° C. 
     
     
         35 . The power semiconductor device of  claim 22 , wherein the insulating layer is a first insulating layer, the power semiconductor device comprising:
 a second insulating layer disposed between the substrate and the first insulating layer; and   a passivation layer disposed over the first insulating layer and the metal layer.   
     
     
         36 . The power semiconductor device of  claim 22 , wherein the substrate is silicon carbide (SiC) substrate, Gallium nitride (GaN) substrate, or Gallium arsenide (GaAs) substrate. 
     
     
         37 . A power semiconductor device, comprising:
 a substrate having an edge;   a first insulating layer disposed over the substrate;   a second insulating layer disposed over the first insulating layer;   a metal layer disposed over the second insulating layer and including a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness;   a passivation layer disposed over the second insulating layer and the metal layer;   a coating layer disposed over the passivation layer and having a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the edge of the substrate and the second portion of the metal layer; and   a protective layer covering the substrate, the first insulating layer, the second insulating layer, the metal layer, the passivation layer, and the coating layer.   
     
     
         38 . The power semiconductor device of  claim 37 , wherein the first thickness of the first portion is in a range from 20% to 60% of the second thickness of the second portion. 
     
     
         39 . A power semiconductor device, comprising:
 a substrate having an edge;   an insulating layer disposed over the substrate;   a metal layer disposed over the insulating layer and including a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness greater than the first thickness, the second portion being spaced apart from the first portion;   a coating layer disposed over the metal layer and having a third thickness greater than the second thickness, the first portion of the metal layer being disposed between the edge of the substrate and the second portion of the metal layer; and   a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer.   
     
     
         40 . The power semiconductor device of  claim 39 , wherein the second thickness of the second portion is at least 2 μm. 
     
     
         41 . The power semiconductor device of  claim 39 , wherein the third thickness of the coating layer is greater than 9 μm. 
     
     
         42 . The power semiconductor device of  claim 39 , wherein the coating layer includes a plurality of portions that are spaced apart.