Dual Dopant Source/Drain Regions and Methods of Forming Same

Abstract

A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

What is claimed is: 
     
         1 . A device comprising:
 a semiconductor substrate;   a gate stack at a top surface of the semiconductor substrate;   a source/drain region adjacent the gate stack, wherein the source/drain region comprises a first epitaxy region comprising first impurities;   a first doped region comprising second impurities in the first epitaxy region; and   a second doped region comprising third impurities in the first epitaxy region, the second impurities having a lower formation enthalpy than the third impurities, the first doped region surrounding sides of the second doped region such that the second impurities extend from a top of the semiconductor substrate to along sides of the second doped region.   
     
     
         2 . The device of  claim 1 , wherein the source/drain region further comprises a second epitaxy region surrounding the first epitaxy region, wherein the second epitaxy region comprises fourth impurities, and the fourth impurities are a different element than the first impurities. 
     
     
         3 . The device of  claim 1 , wherein the second doped region extends lower than the first doped region. 
     
     
         4 . The device of  claim 1 , wherein the second impurities of the first doped region extend from the top of the semiconductor substrate to below the second doped region. 
     
     
         5 . The device of  claim 1 , wherein the second impurities are arsenic, and the third impurities comprise phosphorus. 
     
     
         6 . The device of  claim 1 , wherein a concentration of the third impurities in the second doped region increases in a direction towards a top surface of the source/drain region. 
     
     
         7 . The device of  claim 1  further comprising a source/drain contact extending into the second doped region, wherein a concentration of the third impurities at the source/drain contact is at least 10 23  cm −3 . 
     
     
         8 . A device comprising:
 a gate stack at a top surface a semiconductor substrate;   a source/drain region adjacent the gate stack, wherein the source/drain region comprises:
 a first epitaxy region comprising first impurities; 
 a second epitaxy region extending along sidewalls and below the first epitaxy region, the second epitaxy region comprising second impurities different from the first impurities; 
   an arsenic-doped region extending into the first epitaxy region; and   a phosphorus-doped region extending into the first epitaxy region, wherein arsenic of the arsenic-doped region extends along sides and below the phosphorus-doped region.   
     
     
         9 . The device of  claim 8 , wherein the phosphorus-doped region comprises phosphorus dimer. 
     
     
         10 . The device of  claim 8 , wherein the arsenic-doped region further extends into the second epitaxy region. 
     
     
         11 . The device of  claim 8 , wherein the phosphorus-doped region further extends into the second epitaxy region. 
     
     
         12 . The device of  claim 8 , wherein the first impurities are phosphorus. 
     
     
         13 . The device of  claim 12 , wherein the second impurities are arsenic. 
     
     
         14 . The device of  claim 8  further comprising a gate spacer along sidewalls of the gate stack, wherein the gate spacer overlaps both the arsenic-doped region and the phosphorus-doped region. 
     
     
         15 . A device comprising:
 a gate stack at a top surface a semiconductor substrate;   a source/drain region adjacent the gate stack, wherein the source/drain region comprises a first epitaxy region comprising first n-type dopants;   an arsenic-doped region extending into the first epitaxy region; and   a phosphorus-doped region extending into the first epitaxy region, wherein arsenic of the arsenic-doped region extends along sides of the phosphorus-doped region, and wherein the arsenic of the arsenic-doped region further extends directly under the gate stack.   
     
     
         16 . The device of  claim 15 , wherein the source/drain region further comprises a second epitaxy region extending along sidewalls and below the first epitaxy region, the second epitaxy region comprising second n-type dopants different from the first n-type dopants. 
     
     
         17 . The device of  claim 15 , wherein phosphorus of the phosphorus-doped region extends directly under a gate spacer, the gate spacer being disposed on a sidewall of the gate stack. 
     
     
         18 . The device of  claim 17 , the phosphorus of the phosphorus-doped region further extends directly under the gate stack. 
     
     
         19 . The device of  claim 15 , wherein phosphorus of the phosphorus-doped region extends lower than the arsenic of the arsenic-doped region. 
     
     
         20 . The device of  claim 15 , wherein an phosphorus concentration of the phosphorus-doped region increases in a direction towards a top surface of the source/drain region.