Semiconductor Device and Method

Abstract

Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH3).

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a shallow trench isolation region on a semiconductor substrate;   a gate stack on the shallow trench isolation region; and   an interlayer dielectric on the shallow trench isolation region and the gate stack, wherein the interlayer dielectric comprises a first rounded profile extending into the shallow trench isolation region to a first depth below a top surface of the shallow trench isolation region and a second rounded profile extending into the shallow trench isolation region from the second rounded profile to a second depth below the top surface of the shallow trench isolation region.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a first fin extending from the semiconductor substrate; and   a second fin extending from the semiconductor substrate, wherein the interlayer dielectric extends into the shallow trench isolation region to a third depth below the top surface of the shallow trench isolation region between the first fin and the second fin, wherein the interlayer dielectric extends into the shallow trench isolation region to a fourth depth below the top surface of the shallow trench isolation region outside the first fin and the second fin, and wherein the fourth depth is greater than the third depth.   
     
     
         3 . The semiconductor device of  claim 2 , wherein the interlayer dielectric comprises a third rounded profile extending into the shallow trench isolation region to a fourth depth, and wherein the interlayer dielectric comprises a fourth rounded profile extending into the shallow trench isolation region from the first rounded profile to a fifth depth below the top surface of the shallow trench isolation region. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the third depth is 5 nm to 10 nm, wherein the fourth depth is 10 nm to 20 nm, and wherein the fifth depth is from 15 nm to 25 nm. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the first depth is 10 nm to 20 nm, and wherein the second depth is from 15 nm to 25 nm. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising a gate spacer adjacent the gate stack, wherein the interlayer dielectric extends under the gate spacer in a direction parallel to a major surface of the semiconductor substrate. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the shallow trench isolation region is doped to a phosphorous concentration of at least 1×10 15  atoms/cm 3 . 
     
     
         8 . A semiconductor device comprising:
 a semiconductor fin extending from a semiconductor substrate;   a first gate stack on the semiconductor fin;   a source/drain region in the semiconductor fin adjacent the first gate stack;   an interlayer dielectric (ILD) on the semiconductor fin, the first gate stack, and the source/drain region, the ILD comprising a first rounded portion extending below a bottom surface of the first gate stack, the first rounded portion having a first width, the ILD further comprising a second rounded portion extending below the first rounded portion, the second rounded portion having a second width less than the first width; and   a source/drain contact extending in the ILD and electrically coupled to the source/drain region.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the source/drain contact extends a first distance below the bottom surface of the first gate stack. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the first distance is from 6 nm to 9 nm. 
     
     
         11 . The semiconductor device of  claim 8 , further comprising:
 a second gate stack parallel to the first gate stack;   a first gate spacer along a side surface of the first gate stack; and   a second gate spacer along a side surface of the second gate stack, wherein the first width is greater than a third width between the first gate spacer and the second gate spacer.   
     
     
         12 . The semiconductor device of  claim 8 , wherein the first rounded portion extends to a first depth below the bottom surface of the first gate stack from 10 nm to 20 nm, and wherein the second rounded portion extends to a second depth below the bottom surface of the first gate stack from 15 nm to 25 nm. 
     
     
         13 . The semiconductor device of  claim 8 , further comprising a shallow trench isolation (STI) region adjacent the semiconductor fin, wherein the ILD extends into the STI region, wherein the STI region comprises boron impurities with a concentration of at least 1×10 15  atoms/cm 3 . 
     
     
         14 . A semiconductor device comprising:
 a shallow trench isolation (STI) region over a semiconductor substrate;   a gate electrode over the STI region; and   a first dielectric over the STI region and surrounding the gate electrode, the first dielectric having a first rounded profile extending below a top surface of the STI region a first distance from 5 nm to 25 nm, the first dielectric having a second rounded profile extending from the first rounded profile below a top surface of the STI region a second distance from 10 nm to 30 nm.   
     
     
         15 . The semiconductor device of  claim 14 , further comprising a gate spacer adjacent the gate electrode, the first dielectric extending under the gate spacer a lateral distance from 3 nm to 5 nm. 
     
     
         16 . The semiconductor device of  claim 14 , wherein the STI region is doped with phosphorous. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the STI region is doped with phosphorous to a dopant concentration of at least 1×10 15  atoms/cm 3 . 
     
     
         18 . The semiconductor device of  claim 14 , wherein the first rounded profile has a maximum width from 25 nm to 30 nm, and wherein the second rounded profile has a maximum width from 5 nm to 10 nm. 
     
     
         19 . The semiconductor device of  claim 14 , wherein the first dielectric comprises a contact etch stop layer (CESL) and an interlayer dielectric (ILD) over the CESL. 
     
     
         20 . The semiconductor device of  claim 14 , further comprising a source/drain contact extending at least partially through the first dielectric, wherein a bottom surface of the source/drain contact is disposed below a top surface of the STI region.