Methods for fabrication of bonded wafers and surface acoustic wave devices using same

Abstract

A method of fabricating a bonded wafer with low carrier lifetime in silicon comprises providing a silicon substrate having opposing top and bottom surfaces, modifying a top portion of the silicon substrate to reduce carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion, bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate, and providing a pair of electrodes having fingers that are inter-digitally dispersed on a top surface of the piezoelectric layer, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. The modifying and bonding steps may be performed in any order. The modified top portion of the silicon substrate prevents the creation of a parasitic conductance within that portion during operation of the SAW device.

What is claimed is: 
     
         1 . A method of fabricating a bonded wafer with low carrier lifetime in silicon, the method comprising:
 providing a silicon substrate having opposing top and bottom surfaces;   modifying a top portion of the silicon substrate to impair an ability of the top portion to behave like a semiconductor by forming locations across a thickness of the top portion which trap free carriers;   bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate; and   providing a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device, the modified top portion of the silicon substrate preventing creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device.   
     
     
         2 . The method of  claim 1  wherein the thickness of the modified top portion is at least 10 nanometers. 
     
     
         3 . The method of  claim 1  wherein the thickness of the modified top portion is at least 50 nanometers. 
     
     
         4 . The method of  claim 1  wherein the thickness of the modified top portion is at least 200 nanometers. 
     
     
         5 . The method of  claim 1  wherein providing the piezoelectric layer comprises providing a layer comprising at least one of quartz, lithium niobate (LiNbO 3 ), or lithium tantalate (LiTaO 3 ). 
     
     
         6 . The method of  claim 1  wherein T<(2*D). 
     
     
         7 . The method of  claim 1  wherein T>(0.10*D). 
     
     
         8 . The method of  claim 1  wherein:
     T <(1.76−2.52 e -4*( V   SUB +4210− V   PIEZO ))* D;  
 
 V SUB  is a velocity of a slowest acoustic wave in a propagation direction in the silicon substrate; and 
 V PIEZO  is a SAW velocity in the piezoelectric layer. 
 
     
     
         9 . A method of fabricating a bonded wafer with low carrier lifetime in silicon, the method comprising:
 providing a silicon substrate having opposing top and bottom surfaces;   modifying a top portion of the silicon substrate to impair an ability of the top portion to behave like a semiconductor by forming locations in the top portion which trap free carriers;   bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate; and   providing a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device, the modified top portion of the silicon substrate preventing creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device;   wherein the modifying and bonding steps are performed in any order.   
     
     
         10 . The method of  claim 9  wherein the silicon substrate is monocrystalline and wherein modifying the top portion of the silicon substrate comprises modifying the top portion to comprise a non-monocrystalline structure having the locations which trap free carriers. 
     
     
         11 . The method of  claim 10  wherein the top portion is modified to have a defect density in a range from 1e17/cm 3  to 1e22/cm 3 . 
     
     
         12 . The method of  claim 10  wherein modifying the top portion of the silicon substrate comprises modification by damage implantation. 
     
     
         13 . The method of  claim 12  wherein the modification by damage implantation is performed across a thickness of the top portion of the silicon substrate. 
     
     
         14 . The method of  claim 12  wherein the damage implantation is performed to cause a defect density in a range from 1e17/cm 3  to 1e22/cm 3 . 
     
     
         15 . The method of  claim 10  wherein modifying the top portion of the silicon substrate comprises modification by growth or deposition of polycrystalline silicon, nanocrystalline silicon, and/or amorphous silicon. 
     
     
         16 . The method of  claim 9  wherein modifying the top portion of the silicon substrate comprises modification by inclusion of deep trap impurities. 
     
     
         17 . The method of  claim 16  wherein the top portion is modified to have an impurity density in a range from 1e15/cm 3  to 1e18/cm 3 . 
     
     
         18 . The method of  claim 9  wherein the modified top portion has a carrier lifetime of less than 100 nanoseconds. 
     
     
         19 . A method of fabricating a bonded wafer with low carrier lifetime in silicon, the method comprising:
 providing a silicon substrate having opposing top and bottom surfaces;   modifying a top portion of the silicon substrate to reduce carrier lifetime across a thickness of the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion;   bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate; and   providing a pair of electrodes having fingers that are inter-digitally dispersed on the top surface of the piezoelectric layer in a pattern having a center-to-center distance D between adjacent fingers of the same electrode, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device, the modified top portion of the silicon substrate preventing creation of a parasitic conductance within the top portion of the silicon substrate during operation of the SAW device.   
     
     
         20 . The method of  claim 19  further comprising providing an insulation layer between the silicon substrate and the piezoelectric layer, wherein the modifying and providing the insulation layer steps are performed in any order. 
     
     
         21 . The method of  claim 20  wherein providing the insulation layer comprises providing a layer of silicon oxide. 
     
     
         22 . The method of  claim 21  further comprising doping the layer of silicon dioxide with Fluorine or Boron compounds to reduce thermal sensitivity of the SAW device. 
     
     
         23 . The method of  claim 20  wherein a thickness of the insulation layer is greater than (0.02*D). 
     
     
         24 . The method of  claim 23  wherein providing the insulation layer comprises providing a layer of silicon oxide. 
     
     
         25 . The method of  claim 20  wherein:
     T <(1.76−2.52 e -4*( V   SUB +4210− V   PIEZO )−(0.50* T   I ))* D;  
 
 V SUB  is a velocity of a slowest acoustic wave in a propagation direction in the silicon substrate; 
 V PIEZO  is a SAW velocity in the piezoelectric layer; and 
 T I  is a thickness of the insulation layer. 
 
     
     
         26 . The method of  claim 20  wherein a thickness of the insulation layer is less than (0.1*D). 
     
     
         27 . The method of  claim 19  further comprising embedding or covering the pair of electrodes by at least one dielectric, insulation, or passivation layer. 
     
     
         28 . The method of  claim 27  further comprising doping the at least one dielectric, insulation, or passivation layer with Fluorine or Boron compounds. 
     
     
         29 . The method of  claim 28  wherein doping the at least one of the insulation layer, the dielectric layer, or the passivation layer with Fluorine or Boron compounds reduces thermal sensitivity of the SAW device.