Mitigation of time dependent dielectric breakdown

Abstract

The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.

What is claimed is: 
     
         1 . A method, comprising:
 forming a dielectric layer having a first opening on a substrate;   forming a gate metal stack in the first opening and on the dielectric layer, wherein the gate metal stack forms a second opening in the first opening;   forming a spacer layer on the gate metal stack;   etching the spacer layer to form spacers on sidewall surfaces of the second opening, wherein the spacers form a third opening in the second opening; and   depositing a metal fill layer on the spacers and the gate metal stack to fill the third opening, wherein the metal fill layer is in contact with the gate metal stack in the third opening.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming an interfacial layer on a bottom surface of the first opening; and   depositing a high-k dielectric in the first opening, wherein the high-k dielectric is in contact with the interfacial layer and in contact with the sidewall surfaces of the first opening.   
     
     
         3 . The method of  claim 1 , wherein forming the metal gate stack comprises:
 depositing a capping layer in the first opening; and   depositing a work-function metal stack on the capping layer.   
     
     
         4 . The method of  claim 1 , wherein etching the spacer layer to form the spacers comprises:
 removing the spacer layer from a top surface of the dielectric layer; and   removing the spacer layer from a bottom of the first opening.   
     
     
         5 . The method of  claim 1 , wherein forming the spacer layer comprises depositing a dielectric material to fill the second opening, wherein the dielectric material comprises silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), or silicon oxycarbide (SiO x C y ). 
     
     
         6 . The method of  claim 1 , wherein forming the spacer layer comprises depositing a silicon-based layer comprising nitrogen to fill the second opening. 
     
     
         7 . The method of  claim 1 , wherein forming the spacer layer comprises depositing a silicon-based layer comprising carbon to fill the second opening. 
     
     
         8 . The method of  claim 1 , wherein depositing the metal fill layer comprises:
 depositing a barrier layer on the spacers and the gate metal stack; and   depositing a metal on the barrier layer.   
     
     
         9 . A method, comprising:
 forming a pair of spacers on a substrate, wherein the pair of spacers are opposite to each other;   forming a dielectric layer on the substrate and the pair of spacers;   forming a gate metal stack on the dielectric layer and over the pair of spacers, wherein the gate metal stack forms a first recess;   forming a spacer layer on side surfaces of the first recess, wherein the spacer layer forms a second recess that exposes a bottom surface of the first recess; and   filling the second recess with a metal.   
     
     
         10 . The method of  claim 9 , wherein forming the spacer layer comprises:
 blanket depositing a dielectric material in the first recess and on the gate metal stack; and   etching the deposited dielectric material with an anisotropic etch.   
     
     
         11 . The method of  claim 10 , wherein etching the deposited dielectric material comprises removing the deposited dielectric material on horizontal surfaces of the gate metal stack. 
     
     
         12 . The method of  claim 9 , wherein forming the spacer layer comprises filling the first recess with a silicon nitride-based dielectric material. 
     
     
         13 . The method of  claim 9 , wherein forming the gate metal stack comprises conformally depositing the gate metal stack on bottom and sidewall surfaces of the dielectric layer. 
     
     
         14 . The method of  claim 9 , wherein filling the second recess with the metal comprises depositing the metal on the spacer layer and the gate metal stack. 
     
     
         15 . The method of  claim 9 , further comprising planarizing top surfaces of the dielectric layer, the gate metal stack, the spacer layer, and the filled metal. 
     
     
         16 . A semiconductor structure, comprises:
 a pair of spacers on a substrate, wherein the pair of spacers are opposite to each other;   a dielectric layer on the substrate between the pair of spacers, wherein the dielectric layer forms a first opening;   a gate metal stack on the dielectric layer and in the first opening, wherein the gate metal stack forms a second opening;   a spacer layer on side surfaces of the second opening and in contact with the gate metal stack, wherein the spacer layer forms a third opening exposing a bottom surface of the gate metal stack; and   a metal in the third opening.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein the gate metal stack is in contact with the bottom surface of the gate metal stack. 
     
     
         18 . The semiconductor structure of  claim 16 , wherein top surfaces of the dielectric layer, the gate metal stack, the spacer layer, and the metal are co-planar. 
     
     
         19 . The semiconductor structure of  claim 16 , wherein the gate metal stack is interposed between the spacer layer and the dielectric layer. 
     
     
         20 . The semiconductor structure of  claim 16 , wherein the spacer layer is interposed between the gate metal stack and the metal.