Strained Channel Field Effect Transistor

Abstract

Various strained channel transistors are disclosed herein. An exemplary semiconductor device includes a substrate and a fin structure disposed over the substrate. The fin structure includes a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The second epitaxial layer includes a relaxed transversal stress component and a longitudinal compressive stress component, and the third epitaxial layer has uni-axial strain. A gate structure is disposed on a channel region of the fin structure, such that the gate structure interposes a source region and a drain region of the fin structure.

What is claimed is: 
     
         1 . A method comprising:
 forming a dielectric layer over a semiconductor substrate;   forming a trench in the dielectric layer;   forming a first semiconductor layer in the trench over the semiconductor substrate;   forming a second semiconductor layer in the trench over the first semiconductor layer, wherein the first semiconductor layer has a first composition, the second semiconductor layer has a second composition different than the first composition of the first semiconductor layer, and the second semiconductor layer includes germanium; and   etching back the dielectric layer to expose a portion of the second semiconductor layer.   
     
     
         2 . The method of  claim 1 , further comprising forming a gate structure that is disposed over a top surface and sidewall surfaces of a channel portion of the exposed portion of the second semiconductor layer. 
     
     
         3 . The method of  claim 1 , further comprising forming a third semiconductor layer over the second semiconductor layer that wraps the exposed portion of the second semiconductor layer, wherein the third semiconductor layer has a third composition that is different than the second composition of the second semiconductor layer. 
     
     
         4 . The method of  claim 3 , further comprising forming a gate structure that is disposed over a top surface and sidewall surfaces of a portion of the third semiconductor layer. 
     
     
         5 . The method of  claim 1 , wherein the forming the first semiconductor layer includes performing a first epitaxial growth process and the forming the second semiconductor layer includes performing a second epitaxial growth process. 
     
     
         6 . The method of  claim 1 , wherein the first semiconductor layer includes germanium and the second semiconductor layer includes silicon and germanium. 
     
     
         7 . The method of  claim 1 , wherein the first semiconductor layer includes silicon and germanium and the second semiconductor layer includes germanium. 
     
     
         8 . The method of  claim 1 , wherein the first semiconductor layer is relaxed, and the second semiconductor layer is strained along one direction. 
     
     
         9 . The method of  claim 1 , wherein the etching back the dielectric layer includes performing an anisotropic etch on the dielectric layer. 
     
     
         10 . A method comprising:
 epitaxially growing a germanium-comprising layer over a germanium-comprising substrate extension from a semiconductor substrate, wherein the germanium-comprising substrate extension is disposed between a first isolation feature and a second isolation feature and the germanium-comprising substrate extension has a first composition and the germanium-comprising layer has a second composition that is different than the first composition;   etching back the first isolation feature and the second isolation feature after forming the germanium-comprising layer; and   forming a gate over a top surface and sidewall surfaces of a channel portion of the germanium-comprising layer.   
     
     
         11 . The method of  claim 10 , further comprising forming the germanium-comprising substrate extension by doping a portion of the semiconductor substrate. 
     
     
         12 . The method of  claim 10 , wherein the germanium-comprising layer is a first germanium-comprising layer, the method further comprising epitaxially growing a second germanium-comprising layer over the first germanium-comprising layer before the etching back. 
     
     
         13 . The method of  claim 10 , wherein the germanium-comprising layer is a first germanium-comprising layer, the method further comprising epitaxially growing a second germanium-comprising layer over the first germanium-comprising layer after the etching back. 
     
     
         14 . The method of  claim 10 , wherein the etching back is performed on the first isolation feature and the second isolation feature until a height of the germanium-comprising layer above the first isolation feature and the second isolation feature is about 10 nm. 
     
     
         15 . The method of  claim 14 , wherein a length of the germanium-comprising layer is at least 100 nm and a ratio of a width of the germanium-comprising layer to a length of the germanium-comprising layer is about 1:5 to about 1:10. 
     
     
         16 . The method of  claim 10 , wherein the first isolation feature and the second isolation feature physically contact sidewalls of the germanium-comprising substrate extension and tops of the semiconductor substrate. 
     
     
         17 . A device comprising:
 a dielectric layer disposed on a silicon substrate;   a silicon fin extending from the silicon substrate and through the dielectric layer, wherein the silicon fin extends a height above the dielectric layer;   a stressed silicon germanium layer disposed over the dielectric layer and the silicon fin, wherein the stressed silicon germanium layer wraps an entirety of a portion of the silicon fin that extends the height above the dielectric layer, such that the stressed silicon germanium layer covers a first sidewall, a second sidewall, and a top of the portion of the silicon fin; and   a gate that wraps a portion of the stressed silicon germanium layer, wherein the portion of the stressed silicon germanium layer provides a channel.   
     
     
         18 . The device of  claim 17 , wherein the gate is a first gate and the channel is a second channel, the device further comprising:
 a silicon germanium fin extending from the silicon substrate and through the dielectric layer, wherein the silicon germanium fin extends the height above the dielectric layer;   a stressed silicon layer disposed over the dielectric layer and the silicon germanium fin, wherein the stressed silicon layer wraps an entirety of a portion of the silicon germanium fin that extends the height above the dielectric layer, such that the stressed silicon layer covers a first sidewall, a second sidewall, and a top of the portion of the silicon germanium fin; and   a second gate that wraps a portion of the stressed silicon layer, wherein the portion of the stressed silicon layer provides a second channel.   
     
     
         19 . The device of  claim 17 , wherein the stressed silicon germanium layer is a first stressed silicon germanium layer, the gate is a first gate, and the channel is a second channel, wherein the device further comprises:
 a germanium fin extending from the silicon substrate and through the dielectric layer, wherein the germanium fin extends the height above the dielectric layer;   a second stressed silicon germanium layer disposed over the dielectric layer and the germanium fin, wherein the second stressed silicon germanium layer wraps an entirety of a portion of the germanium fin that extends the height above the dielectric layer, such that the second stressed silicon germanium layer covers a first sidewall, a second sidewall, and a top of the portion of the germanium fin; and   a second gate that wraps a portion of the second stressed silicon germanium layer, wherein the portion of the second stressed silicon germanium layer provides a second channel.   
     
     
         20 . The device of  claim 19 , wherein the first stressed silicon germanium layer has compressive stress and the second stressed silicon germanium layer has tensile stress.