Hybrid Sram Design With Nano-Structures

Abstract

A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.

What is claimed is: 
     
         1 . A method, comprising:
 forming a stack that includes a plurality of semiconductive layers and a plurality of sacrificial layers in an NMOS region of a semiconductor device, wherein the semiconductive layers interleave with the sacrificial layers;   removing the sacrificial layers in the NMOS region without substantially removing the semiconductive layers, thereby forming nano-structure channels;   after the removing of the sacrificial layers, forming a first gate structure over and circumferentially around each of the semiconductive layers in the NMOS region;   forming a fin structure in a PMOS region of the semiconductor device; and   forming a second gate structure that partially wraps around the fin structure;   wherein:   the fin structure has a fin width and is separated from an adjacent fin structure by a fin pitch; and   a maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch.   
     
     
         2 . The method of  claim 1 , wherein:
 the semiconductor device includes a Static Random Access Memory (SRAM) device that includes a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass-gate (PG) transistor;   the forming the stack, the removing the sacrificial layers, and the forming the first gate structure are performed to fabricate the PD transistor or the PG transistor; and   the forming the fin structure and the forming the second gate structure are performed to fabricate the PU transistor.   
     
     
         3 . The method of  claim 1 , further comprising: shaping the semiconductive layers such that the semiconductive layers have unequal widths among one another. 
     
     
         4 . The method of  claim 3 , wherein the shaping is performed such that a bottommost one of the semiconductive layers has a greatest width while a topmost one of the semiconductive layers has a smallest width. 
     
     
         5 . The method of  claim 3 , wherein the shaping is performed such that a bottommost one of the semiconductive layers has a smallest width while a topmost one of the semiconductive layers has a greatest width. 
     
     
         6 . The method of  claim 1 , wherein: the maximum channel width is formed to be in a range between about 1-15 times of the fin width. 
     
     
         7 . The method of  claim 1 , wherein: the maximum channel width is formed to be in a range within about 20%-100% of the sum of: the fin width and the fin pitch. 
     
     
         8 . The method of  claim 1 , wherein the forming the stack and the forming the fin structure are performed such that an uppermost one of the nano-structure channels is formed to have a more vertically elevated upper surface than the fin structure. 
     
     
         9 . The method of  claim 1 , wherein:
 the fin structure extends in a first horizontal direction; and   the fin width, the fin pitch, and the maximum channel width are measured in a second horizontal direction that is different from the first horizontal direction.   
     
     
         10 . The method of  claim 1 , wherein the forming the nano-structure channels includes shaping the nano-structure channels as nano-sheets, nano-bars, or nano-wires. 
     
     
         11 . A method, comprising:
 forming, in an NMOS region of a semiconductor device, a stack of nano-structure channels and sacrificial layers that interleave with one another vertically, wherein an uppermost one of the nano-structure channels has a first height;   etching away the sacrificial layers in the stack while preserving the nano-structure channels;   forming a first gate over and circumferentially around each of the nano-structure channels;   forming a vertically protruding fin structure in a PMOS region of the semiconductor device, wherein an uppermost surface of the fin structure has a second height that is less than the first height; and   forming a second gate that partially wraps around the fin structure.   
     
     
         12 . The method of  claim 11 , wherein:
 the fin structure has a first lateral dimension and is separated from an adjacent fin structure by a second lateral dimension; and   a third lateral dimension of the nano-structure channels is less than or equal to a sum of: the first lateral dimension and the second lateral dimension.   
     
     
         13 . The method of  claim 12 , wherein:
 the fin structure extends in a first horizontal direction; and   the first lateral dimension, the second lateral dimension, and the third lateral dimension are each measured in a second horizontal direction that is perpendicular to the first horizontal direction.   
     
     
         14 . The method of  claim 12 , wherein the third lateral dimension is formed to be in a range between about 20% and about 100% of the sum of the first lateral dimension and the second lateral dimension. 
     
     
         15 . The method of  claim 12 , wherein the third lateral dimension is formed to be in a range between about 1-15 times of the second lateral dimension. 
     
     
         16 . The method of  claim 11 , further comprising: shaping the nano-structure channels such that the nano-structure channels have different lateral dimensions. 
     
     
         17 . The method of  claim 11 , wherein:
 the semiconductor device includes a Static Random Access Memory (SRAM) device that includes a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass-gate (PG) transistor;   the forming the stack, the etching away, and the forming the first gate are performed to fabricate the PD transistor or the PG transistor; and   the forming the fin structure and the forming the second gate are performed to fabricate the PU transistor.   
     
     
         18 . A method, comprising:
 forming a first stack in a first region and a second stack in a second region of a semiconductor device, wherein the first stack and the second stack each includes a plurality of semiconductive layers and a plurality of sacrificial layers that interleave with the semiconductive layers;   etching back the second stack so as to remove at least a subset of the semiconductive layers and sacrificial layers in the second stack, while the semiconductive layers in the first stack are substantially unaffected by the etching back;   removing the sacrificial layers in the first stack and removing the sacrificial layers in the second stack without substantially affecting the semiconductive layers in the first stack and in the second stack; and   forming gate structures over and circumferentially around the semiconductive layers in the first stack and in the second stack.   
     
     
         19 . The method of  claim 18 , wherein:
 the forming the first stack and the second stack, the etching back, the removing the sacrificial layers, and the forming the gate structures are fabrication processes for fabricating a Static Random Access Memory (SRAM) device that includes a pull-up (PU) transistor in the second region, a pull-down (PD) transistor in the first region, and a pass-gate (PG) transistor in the first region;   the first stack is formed in the first region but not in the second region; and   the second stack is formed in the second region but not in the first region.   
     
     
         20 . The method of  claim 18 , further comprising: shaping the semiconductive layers in at least the first stack such that the semiconductive layers in the first stack are formed to have different lateral dimensions among one another.