Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices

Abstract

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

1 . A memory cell comprising:
 a wordline;   a first bitline;   a second bitline; and   a memory element electrically connected to the wordline and selectively electrically connected to the first bitline and to the second bitline, the memory element storing information via a resistive state of the memory element;   wherein the memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.   
     
     
         2 . The memory cell of  claim 1  wherein:
 the memory cell further comprises a first diode and a second diode; 
 the memory element comprises a first electrode connected to the first bitline via the first diode and to the second bitline via the second diode and a second electrode connected to the wordline; and 
 the memory element is electrically connected to the first bitline via the first diode when the first diode is forward biased and is electrically disconnected from the first bitline when the first diode is not forward biased; and 
 the memory element is electrically connected to the second bitline via the second diode when the second diode is forward biased and is electrically disconnected from the second bitline when the second diode is not forward biased. 
 
     
     
         3 . The memory cell of  claim 1  wherein the memory element comprises at least one of an ionic conducting chalcogenide, a binary metal oxide, a perovskite oxide, a colossal magnetoresistive, or a polymer. 
     
     
         4 . The memory cell of  claim 1  wherein the memory element is configured to store the information in a non-volatile manner in the absence of a voltage or a current. 
     
     
         5 . A memory cell programming method comprising:
 providing a memory cell comprising a wordline, first and second bitlines, and a memory element, the memory element being electrically connected to the wordline and selectively electrically connected to the first and second bitlines;   using the memory element, storing information via a first resistive state of the memory element;   applying a first voltage across the wordline and the first bitline effective to electrically disconnect the first bitline from the memory element; and   applying a second voltage across the wordline and the second bitline effective to electrically connect the second bitline to the memory element and to configure the memory element in a different second resistive state.   
     
     
         6 . The method of  claim 5  further comprising:
 providing a first diode connected to a first electrode of the memory element and to the first bitline, the first diode being reverse biased due to the first voltage and the first voltage being less than a breakdown voltage of the first diode; and 
 providing a second diode connected to the first electrode of the memory element and to the second bitline; 
 wherein:
 a second electrode of the memory element is connected to the wordline; 
 the memory element is highly conductive of current between the second electrode and the first electrode when the memory element is in the first resistive state; and 
 the memory element is highly resistive of current between the second electrode and the first electrode when the memory element is in the second resistive state. 
 
 
     
     
         7 . The method of  claim 6  wherein the applied second voltage is greater than a sum of a turn-off voltage of the memory element and a cut-in voltage of the second diode. 
     
     
         8 . The method of  claim 5  wherein the applied first voltage is substantially the same as the applied second voltage. 
     
     
         9 . The method of  claim 5  further comprising subsequent to the applying of the first voltage and the applying of the second voltage:
 applying a third voltage across the second bitline and the wordline effective to electrically disconnect the second bitline from the memory element; and 
 applying a fourth voltage across the first bitline and the wordline effective to electrically connect the first bitline to the memory element and to configure the memory element in the first resistive state. 
 
     
     
         10 . The method of  claim 9  wherein the applied third voltage is substantially the same as the applied fourth voltage. 
     
     
         11 . A memory cell reading method comprising:
 providing a memory cell comprising a wordline, first and second bitlines, and a memory element electrically connected to the wordline and selectively electrically connected to the first and second bitlines, the memory element being disposed to be selectively configured in any of a plurality of different resistive states;   applying a first voltage across the wordline and the first bitline effective to electrically disconnect the first bitline from the memory element;   applying a second voltage across the wordline and the second bitline effective to cause a current to flow from the wordline through the memory element to the second bitline; and   based on the current, determining that the memory element is configured in a particular one of the plurality of different resistive states.   
     
     
         12 . The method of  claim 11  wherein the particular one of the plurality of different resistive states is associated with a value of a bit of information. 
     
     
         13 . The method of  claim 11  wherein the memory element is disposed to be selectively configured in either a high resistance state or a low resistance state. 
     
     
         14 . The method of  claim 11  further comprising:
 providing a first diode connected to a first electrode of the memory element and to the first bitline; and 
 providing a second diode connected to the first electrode of the memory element and to the second bitline; 
 wherein the applied second voltage is greater than a cut-in voltage of the second diode but less than a sum of the cut-in voltage of the second diode and a turn-off voltage of the memory element and the memory element comprises a second electrode connected to the wordline. 
 
     
     
         15 . The method of  claim 11  wherein the determining comprises comparing the current to a reference current. 
     
     
         16 . The method of  claim 11  wherein the determining comprises determining that the current is very small or immeasurable and that the memory element is in a high resistance state. 
     
     
         17 - 25 . (canceled)