Protection Against Timing-based Security Attacks on Re-order Buffers

Abstract

Methods, systems, and apparatuses related to re-order buffers and for protection from timing-based security attacks are described. A processor may have functional units configured to execute instructions out of order, a re-order buffer configured to buffer the execution results of instructions for output in order, and a controller configured to randomize data timing in the re-order buffer. For example, the controller can make random adjustments to the capacity of the re-order buffer in buffering and/or sorting execution results and thus randomize data timing in the re-order buffer.

What is claimed is: 
     
         1 . A device, comprising:
 a buffer having a full capacity;   a random number generator; and   a controller configured to adjust a currently usable capacity of the buffer as a random fraction of the full capacity based on an output of the random number generator.   
     
     
         2 . The device of  claim 1 , wherein the device includes a processor having the buffer, the controller, and one or more functional units. 
     
     
         3 . The device of  claim 2 , wherein the buffer is configured to store results of instructions executed in the one or more functional units out of order relative to a programmed order of the instructions. 
     
     
         4 . The device of  claim 3 , wherein the processor further includes registers; and the processor is further configured to write the results from the buffer to the registers according to the programmed order of the instructions. 
     
     
         5 . The device of  claim 4 , wherein the controller is configured to adjust the currently usable capacity periodically. 
     
     
         6 . The device of  claim 4 , wherein the controller is configured to update the random fraction periodically according to an output of the random number generator. 
     
     
         7 . The device of  claim 4 , wherein the controller is configured to update the random fraction after a random time period. 
     
     
         8 . The device of  claim 4 , wherein the controller is configured to change a timing pattern in results, generated by the instructions and stored in the buffer, by adjusting the random fraction. 
     
     
         9 . The device of  claim 8 , further comprising:
 an instruction buffer, wherein the processor is configured to fetch the instructions into the instruction buffer in accordance the programmed order of the instructions and issue instructions from the instruction buffer to the one or more functional units out of order relative to the programmed order of the instructions.   
     
     
         10 . A processor, comprising:
 a first buffer having a full capacity;   a random number generator; and   a controller configured to adjust a currently usable capacity of the first buffer as a random fraction of the full capacity based on an output of the random number generator.   
     
     
         11 . The processor of  claim 10 , further comprising:
 one or more functional units; and   a second buffer;   wherein the processor is configured to fetch instructions into the second buffer in a first order, and issue the instructions from the second buffer to the one or more functional units in a second order different from the first order; and   wherein the first buffer is configured to store results of execution of the instructions by the one or more functional units as issued from the second buffer.   
     
     
         12 . The processor of  claim 11 , further comprising:
 registers, wherein the processor is further configured to write the results from the first buffer to the registers according to the first order.   
     
     
         13 . The processor of  claim 12 , wherein the controller is configured to adjust the currently usable capacity periodically. 
     
     
         14 . The processor of  claim 12 , wherein the controller is configured to update the random fraction periodically according to an output of the random number generator. 
     
     
         15 . The processor of  claim 12 , wherein the controller is configured to update the random fraction after a random time period. 
     
     
         16 . The processor of  claim 12 , wherein the controller is configured to change a timing pattern in results, generated by execution of the instructions and stored in the first buffer, by adjusting the random fraction. 
     
     
         17 . A method, comprising:
 generating, using a random number generator of a device, an output; and   adjusting, by a controller of the device having a first buffer and based on the output of the random number generator, a currently usable capacity of the first buffer as a random fraction of a full capacity of the first buffer.   
     
     
         18 . The method of  claim 17 , further comprising:
 fetching instructions into a second buffer in a first order;   issuing the instructions from the second buffer to one or more functional units of the device in a second order different from the first order; and   storing, into the first buffer, results of execution of the instructions by the one or more functional units as issued from the second buffer.   
     
     
         19 . The method of  claim 18 , further comprising:
 writing the results from the first buffer to registers of the device according to the first order.   
     
     
         20 . The method of  claim 19 , further comprising:
 updating the random fraction periodically using the random number generator.