Inner Spacers for Gate-All-Around Semiconductor Devices

Abstract

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor that includes a first plurality of channel members, and a second GAA transistor that includes a second plurality of channel members. The first plurality of channel members has a first pitch (P 1 ) and the second plurality of channel members has a second pitch (P 2 ) smaller than the first pitch (P 1 ).

What is claimed is: 
     
         1 . A method, comprising:
 depositing a first semiconductor stack directly on a first area and a second area of a silicon substrate, the first semiconductor stack comprising a first number of channel layers interleaved by a second number of sacrificial layers;   depositing a hard mask layer over the first semiconductor stack directly over the first area;   after the depositing of the hard mask layer, removing the first semiconductor stack directly over the second area;   after the removing, depositing a second semiconductor stack directly over the second area, the second semiconductor stack comprising a third number of channel layers interleaved by a fourth number of sacrificial layers;   removing the hard mask layer;   patterning the first semiconductor stack and a portion of the silicon substrate in the first area to form a first fin-shaped structure having a channel region and a source/drain region and extending along a first direction;   patterning the second semiconductor stack and a portion of the silicon substrate in the second area to form a second fin-shaped structure having a channel region and a source/drain region and extending along the first direction;   forming a first dummy gate stack over the channel region of the first fin-shaped structure and a second dummy gate stack over the channel region of the second fin-shaped structure;   forming a first source/drain feature over the source/drain region of the first fin-shaped structure and a second source/drain feature over the source/drain region of the second fin-shaped structure;   removing the first dummy gate stack and the second dummy gate stack;   selectively removing the second number of sacrificial layers in the channel region of the first fin-shaped structure and the fourth number of sacrificial layers in the channel region of the second fin-shaped structure to form a first number of channel members in the first area and a second number of channel members in the second area; and   forming a first gate structure to wrap around each of the first number of channel members and a second gate structure to wrap around each of the second number of channel members.   
     
     
         2 . The method of  claim 1 , wherein the first number of channel members and the second number of channel members consist essentially of silicon (Si). 
     
     
         3 . The method of  claim 1 , wherein the second number of sacrificial layers and the fourth number of sacrificial layers consist essentially of silicon germanium (SiGe). 
     
     
         4 . The method of  claim 1 ,
 wherein the first number is greater than the third number,   wherein the second number is greater than the fourth number.   
     
     
         5 . The method of  claim 1 ,
 wherein each of the second number of sacrificial layers has a first thickness,   wherein each of the fourth number of sacrificial layers has a second thickness,   wherein the second thickness is greater than the first thickness.   
     
     
         6 . The method of  claim 5 , wherein a ratio of the second thickness to the first thickness is between about 1.1 and 1.5. 
     
     
         7 . The method of  claim 1 ,
 wherein each of the first number of channel layers has a third thickness,   wherein each of the third number of channel layers has a fourth thickness,   wherein the third thickness is substantially equal to the fourth thickness.   
     
     
         8 . The method of  claim 1 , further comprising:
 before the forming of the first source/drain feature and the second source/drain feature, forming gate end dielectric features to reduce lengths of the first dummy gate stack and the second dummy gate stack along a second direction perpendicular to the first direction.   
     
     
         9 . A method, comprising:
 forming a first stack directly on a first area of a semiconductor substrate, the first stack comprising first channel layers interleaved by a first sacrificial layers;   forming a second stack directly on a second area of a semiconductor substrate, the second stack comprising second channel layers interleaved by second sacrificial layers;   patterning the first stack and a portion of the semiconductor substrate in the first area to form a first fin-shaped structure extending along a first direction;   patterning the second stack and a portion of the semiconductor substrate in the second area to form a second fin-shaped structure extending along the first direction;   forming a first dummy gate stack over the first fin-shaped structure and a second dummy gate stack over the second fin-shaped structure;   forming a first source/drain feature adjacent the first dummy gate stack and a second source/drain feature adjacent the second dummy gate stack;   removing the first dummy gate stack and the second dummy gate stack;   selectively removing the first sacrificial layers of the first fin-shaped structure and the second sacrificial layers of the second fin-shaped structure to form first channel members in the first area and second channel members in the second area; and   forming a first gate structure to wrap around each of the first channel members and a second gate structure to wrap around each of the second channel members,   wherein the first gate structure comprises a first gate dielectric layer and the second gate structure comprises a second gate dielectric layer,   wherein the first gate dielectric layer has a first thickness and the second gate dielectric layer has a second thickness greater than the first thickness.   
     
     
         10 . The method of  claim 9 , wherein the semiconductor substrate comprises silicon. 
     
     
         11 . The method of  claim 9 , wherein a ratio of the second thickness to the first thickness is between about 1.3 and about 3.0. 
     
     
         12 . The method of  claim 9 , wherein the first gate dielectric layer and the second gate dielectric layer comprise ZrO, Y 2 O 3 , La 2 O 5 , Gd 2 O 5 , TiO 2 , Ta 2 O 5 , HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, or SrTiO. 
     
     
         13 . The method of  claim 9 ,
 wherein, after the selectively removing the first sacrificial layers and the second sacrificial layers, the first channel members are disposed directly over a first base fin and the second channel members are disposed directly over a second base fin,   wherein the first base fin and the second base fin are formed from the semiconductor substrate.   
     
     
         14 . The method of  claim 13 , wherein, after the forming of the first gate structure and the second gate structure, the first gate structure is in direct contact with the first base fin and the second gate structure is in direct contact with the second base fin. 
     
     
         15 . A method, comprising:
 forming a first plurality of alternating semiconductor layers over a first region and a second region of a substrate, the first plurality of alternating semiconductor layers comprising a first plurality of first semiconductor layers interleaved by a second plurality of second semiconductor layers;   removing the first plurality of alternating semiconductor layers over the first region of the substrate; and   forming a second plurality of alternating semiconductor layers over the first region of the substrate, the second plurality of alternating semiconductor layers comprising a third plurality of first semiconductor layers interleaved by a fourth plurality of second semiconductor layers.   
     
     
         16 . The method of  claim 15 ,
 wherein the first plurality of first semiconductor layers comprises a first layer pitch,   wherein the third plurality of first semiconductor layers comprises a second layer pitch smaller than the first layer pitch.   
     
     
         17 . The method of  claim 15 ,
 wherein each of the second plurality of second semiconductor layers comprises a first layer thickness,   wherein each of the fourth plurality of fourth semiconductor layers comprises a second layer thickness smaller than the first layer thickness.   
     
     
         18 . The method of  claim 15 ,
 wherein the first plurality of first semiconductor layers comprises a first number of first semiconductor layers,   wherein the second plurality of second semiconductor layers comprises a second number of second semiconductor layers,   wherein the first number is smaller than the second number.   
     
     
         19 . The method of  claim 15 , further comprising:
 patterning the second plurality of alternating semiconductor layers over the first region to form a first active region;   patterning the first plurality of alternating semiconductor layers over the second region to form a second active region;   in a first channel region of the first active region, forming a first plurality of channel members out of the first plurality of first semiconductor layers; and   in a second channel region of the second active region, forming a second plurality of channel members out of the third plurality of first semiconductor layers.   
     
     
         20 . The method of  claim 19 , further comprising:
 forming a first gate dielectric layer to a first thickness over the first plurality of channel members; and   forming a second gate dielectric layer to a second thickness over the second plurality of channel members,   wherein the first thickness is greater than the second thickness.