Package structure and manufacturing method thereof

Abstract

A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.

What is claimed is: 
     
         1 . A package structure, comprising:
 a chip package, comprising at least one semiconductor die, a first insulating encapsulation encapsulating the at least one semiconductor die, and a plurality of conductive pillars next to the at least one semiconductor die and penetrating through the first insulating encapsulation, wherein the plurality of conductive pillars are electrically coupled to the at least one semiconductor die, and a height of the plurality of the conductive pillars are greater than a height of the at least one semiconductor die; and   an antenna package, disposed on and electrically coupled to the chip package, wherein the antenna package comprises:
 metallic patterns, embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is substantially coplanar with a third surface of the second insulating encapsulation. 
   
     
     
         2 . The package structure of  claim 1 , wherein the second surface of each of the metallic patterns is accessibly revealed by the third surface of the second insulating encapsulation. 
     
     
         3 . The package structure of  claim 1 , further comprising:
 a connecting film, disposed on a fourth surface of the second insulating encapsulation, wherein the third surface is opposite to the fourth surface, and the connecting film is disposed between the chip package and the antenna package.   
     
     
         4 . The package structure of  claim 3 , wherein two opposite sides of the connecting film physically contact the second insulating encapsulation and the chip package, respectively. 
     
     
         5 . The package structure of  claim 1 , wherein the chip package further comprises:
 a first redistribution circuit structure, disposed between the antenna package and the first insulating encapsulation and electrically coupled to the at least one semiconductor die and the plurality of conductive pillars, wherein the first insulating encapsulation is in physical contact with the first redistribution circuit structure.   
     
     
         6 . The package structure of  claim 5 , wherein the first redistribution circuit structure comprises at least one alignment mark, and the at least one alignment mark comprises a predetermined pattern of a solid metal plate having at least one slit. 
     
     
         7 . The package structure of  claim 6 , wherein a shape of the at least one slit comprises a L-shape, a cross-shape, a circular-shape, a triangular-shape, a rectangular shape, or combinations thereof. 
     
     
         8 . The package structure of  claim 5 , wherein the chip package further comprises:
 a second redistribution circuit structure, disposed on the first insulating encapsulation and electrically coupled to the at least one semiconductor die, wherein the first insulating encapsulation is disposed between the first redistribution circuit and the second redistribution circuit, and the plurality of conductive pillars are connected to and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure; and   conductive elements, disposed on and electrically coupled to the second redistribution circuit structure, wherein the second redistribution circuit structure is disposed between the first insulating encapsulation and the conductive elements.   
     
     
         9 . The package structure of  claim 1 , wherein a sidewall of the antenna package is aligned with a sidewall of the chip package along a stacking direction of the antenna package and the chip package. 
     
     
         10 . The package structure of  claim 1 , wherein a sidewall of the antenna package is distant from a sidewall of the chip package on a direction perpendicular to a stacking direction of the antenna package and the chip package. 
     
     
         11 . A package structure, comprising:
 a first redistribution circuit structure;   at least one semiconductor die, disposed on and electrically coupled to the first redistribution circuit structure;   a plurality of conductive pillars, disposed on and electrically coupled to the first redistribution circuit structure, and next to and electrically coupled to the at least one semiconductor die, wherein a height of the plurality of the conductive pillars are greater than a height of the at least one semiconductor die;   a first insulating encapsulation, encapsulating the at least one semiconductor die and being penetrated by the plurality of conductive pillars;   metallic patterns, disposed on and electrically coupled to the first redistribution circuit structure; and   a second insulating encapsulation, encapsulating the metallic patterns, wherein the first redistribution circuit structure is disposed between the first insulating encapsulation and the second insulating encapsulation,   wherein a sidewall of each of the metallic patterns is wrapped by the second insulating encapsulation, a first surface of each of the metallic patterns is sandwiched between the second insulating encapsulation, and a second surface of each of the metallic patterns is exposed by a first side of the second insulating encapsulation, wherein the first surface is opposite to the second surface along a stacking direction of the first insulating encapsulation and the second insulating encapsulation, and the first surface and the second surface are connected through the sidewall.   
     
     
         12 . The package structure of  claim 11 , further comprising:
 a third insulating encapsulation, disposed between the second insulating encapsulation and the first redistribution circuit structure, wherein a second side of the second insulating encapsulation is covered by the third insulating encapsulation, and the second side is opposite to the first side.   
     
     
         13 . The package structure of  claim 12 , wherein a third side of the second insulating encapsulation is covered by the third insulating encapsulation, and the third side of the second insulating encapsulation connects the first side and the second side. 
     
     
         14 . The package structure of  claim 12 , wherein a lateral size of the third insulating encapsulation is greater than a lateral size of the second insulating encapsulation, and is less than or substantially equal to a lateral size of the at least one semiconductor die. 
     
     
         15 . The package structure of  claim 11 , wherein the first redistribution circuit structure comprises at least one alignment mark having a solid metal plate with at least one slit, and a shape of the at least one slit comprises a L-shape, a cross-shape, a circular-shape, a triangular-shape, a rectangular-shape, or combinations thereof. 
     
     
         16 . The package structure of  claim 11 , further comprising:
 a second redistribution circuit structure, disposed on the first insulating encapsulation and electrically coupled to the at least one semiconductor die, wherein the first insulating encapsulation is disposed between the first redistribution circuit structure and the second redistribution circuit, wherein the plurality of conductive pillars are connected to and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure; and   conductive elements, disposed on and electrically coupled to the second redistribution circuit structure, wherein the second redistribution circuit structure is disposed between the first insulating encapsulation and the conductive elements.   
     
     
         17 . The package structure of  claim 11 , wherein a sidewall of the second insulating encapsulation is aligned with a sidewall of the first insulating encapsulation along a stacking direction of the second insulating encapsulation and the first insulating encapsulation. 
     
     
         18 . The package structure of  claim 11 , wherein a sidewall of the second insulating encapsulation is distant from a sidewall of the first insulating encapsulation on a direction perpendicular to a stacking direction of the second insulating encapsulation and the first insulating encapsulation. 
     
     
         19 . A package structure, comprising:
 a chip package, comprising:
 a plurality of conductive pillars, 
 at least one semiconductor die, laterally disposed next to the plurality of conductive pillars, wherein a height of the plurality of the conductive pillars are greater than a height of the at least one semiconductor die; and 
 a first insulating encapsulation, encapsulating the at least one semiconductor die and the plurality of conductive pillars, the plurality of conductive pillars penetrating through the first insulating encapsulation and being electrically coupled to the at least one semiconductor die; 
   an antenna package, disposed on and electrically coupled to the chip package, wherein the antenna package comprises:
 metallic patterns, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface; 
 a second insulating encapsulation, covering the metallic patterns, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is substantially coplanar with a third surface of the second insulating encapsulation; and 
 a third insulating encapsulation, embedding the second insulating encapsulation, wherein a lateral size of the third insulating encapsulation is greater than a lateral size of the second insulating encapsulation and is less than or substantially equal to a lateral size of the at least one semiconductor die. 
   
     
     
         20 . The package structure of  claim 19 , wherein the chip package further comprises:
 a first redistribution circuit structure, disposed on a first side of the first insulating encapsulation and electrically coupled to the at least one semiconductor die and the plurality of conductive pillars, wherein the first insulating encapsulation is in physical contact with the first redistribution circuit structure;   a second redistribution circuit structure, disposed on a second side of the first insulating encapsulation and electrically coupled to the at least one semiconductor die and the plurality of conductive pillars, wherein the first insulating encapsulation is in physical contact with the second redistribution circuit structure, and the plurality of conductive pillars are connected to and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure, wherein the first side is opposite to the second side; and   conductive elements, disposed on and electrically coupled to the second redistribution circuit structure, wherein the second redistribution circuit structure is disposed between the first insulating encapsulation and the conductive elements,   wherein the first redistribution circuit structure is sandwiched between the antenna package and the first insulating encapsulation.