Microelectronic device substrate formed by additive process

Abstract

A microelectronic device is formed by forming at least a portion of a substrate of the microelectronic device by one or more additive processes. The additive processes may be used to form semiconductor material of the substrate. The additive processes may also be used to form dielectric material structures or electrically conductive structures, such as metal structures, of the substrate. The additive processes are used to form structures of the substrate which would be costly or impractical to form using planar processes. In one aspect, the substrate may include multiple doped semiconductor elements, such as wells or buried layers, having different average doping densities, or depths below a component surface of the substrate. In another aspect, the substrate may include dielectric isolation structures with semiconductor material extending at least partway over and under the dielectric isolation structures. Other structures of the substrate are disclosed.

What is claimed is: 
     
         1 . A method of forming a microelectronic device, comprising:
 forming a first semiconductor material by a first additive process using a first semiconductor precursor in a substrate of the microelectronic device, the first semiconductor material having a first bandgap energy; and   forming a second semiconductor material by a second additive process using a second semiconductor precursor in the substrate, the second semiconductor material having a second bandgap energy that is higher than the first bandgap energy, wherein the second semiconductor material contacts the first semiconductor material.   
     
     
         2 . The method of  claim 1 , wherein:
 the second semiconductor material contacts a dielectric material; and   the first semiconductor material is separated from the dielectric material by the second semiconductor material   
     
     
         3 . The method of  claim 1 , wherein the second semiconductor material consists essentially of silicon and dopants; and
 the first semiconductor material includes silicon and germanium in source and drain regions of a p-channel metal oxide semiconductor (PMOS) transistor.   
     
     
         4 . The method of  claim 1 , wherein the first semiconductor material consists essentially of silicon and dopants; and
 the second semiconductor material includes silicon and carbon in source and drain regions of an n-channel metal oxide semiconductor (NMOS) transistor.   
     
     
         5 . The method of  claim 1 , wherein the microelectronic device is formed on a workpiece having a crystalline structure. 
     
     
         6 . The method of  claim 1 , wherein the first additive process dispenses a combination of an n-type semiconductor precursor, a p-type semiconductor precursor, and an undoped semiconductor precursor in an area for a p-type semiconductor of a substrate of the microelectronic device. 
     
     
         7 . The method of  claim 6 , wherein the p-type semiconductor is located in an area for a logic NMOS transistor, in an area for an analog NMOS transistor, and in an area for a dual vertical PNP bipolar transistor. 
     
     
         8 . The method of  claim 6 , wherein the first additive process dispenses a second combination of the n-type semiconductor precursor, the p-type semiconductor precursor, and the undoped semiconductor precursor in an area for an n-type semiconductor of the substrate. 
     
     
         9 . The method of  claim 8 , wherein the n-type semiconductor is located in an area for a logic PMOS transistor. 
     
     
         10 . The method of  claim 9 , wherein the first additive process dispenses the n-type semiconductor precursor, the p-type semiconductor precursor, and the undoped semiconductor precursor in sublayers, which are each heated by a first heating process to convert each sublayer into the corresponding p-type semiconductor or n-type semiconductor. 
     
     
         11 . The method of  claim 10 , wherein the first heating process is implemented as a scanned localized heating process. 
     
     
         12 . The method of  claim 10 , wherein the first heating process is implemented as a blanket heating process. 
     
     
         13 . The method of  claim 1 , wherein the second additive process dispenses a dielectric precursor in areas for first isolation structures and second isolation structures in the substrate. 
     
     
         14 . The method of  claim 13 , wherein a second heating process converts the dielectric precursor to a dielectric material to form the first isolation structures and the second isolation structures. 
     
     
         15 . The method of  claim 14 , wherein the second heating process is implemented as a scanned localized heating process. 
     
     
         16 . The method of  claim 14 , wherein the second heating process is implemented as a blanket heating process.