Apparatus and method for scaling pre-scaled results of complex mutiply-accumulate operations on packed real and imaginary data elements

Abstract

An apparatus and method for performing a transform on complex data. For example, one embodiment of a processor comprises: multiplier circuitry to multiply packed real N-bit data elements in the first source register with packed real M-bit data elements in the second source register and to multiply packed imaginary N-bit data elements in the first source register with packed imaginary M-bit data elements in the second source register to generate at least four real products, adder circuitry to subtract a first selected real product from a second selected real product to generate a first temporary result and to subtract a third selected real product from a fourth selected real product to generate a second temporary result, the adder circuitry to add the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, to subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, to add the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and to subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; scaling circuitry to scale the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results; and a destination register to store the first, second, third, and fourth final results in specified data element positions.

1 .- 33 . (canceled) 
     
     
         34 . A method comprising:
 decoding a first instruction to generate a decoded instruction;   storing a first plurality of packed N-bit real and imaginary data elements in a first source register;   storing a second plurality of packed M-bit real and imaginary data elements in a second source register;   storing a third plurality of packed N-bit real and imaginary data elements in a third source register;   multiplying packed real N-bit data elements in the first source register with packed imaginary M-bit data elements in the second source register and multiplying packed imaginary N-bit data elements in the first source register with packed real M-bit data elements in the second source register to generate at least four imaginary products;   adding a first selected imaginary product and a second selected imaginary product to generate a first temporary result and to adding a third selected imaginary product and a fourth selected imaginary product to generate a second temporary result   adding the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, subtracting the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result;   scaling the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results; and   storing the first, second, third, and fourth final results in specified data element positions.   
     
     
         35 . The method of  claim 34 , wherein the scaling is performed in accordance with bit values in an immediate of the first instruction. 
     
     
         36 . The method of  claim 35 , wherein the immediate bit values comprise a first value to indicate no shifting, a second value to indicate a 1-bit shift, and a third value to indicate a 2-bit shift. 
     
     
         37 . The method of  claim 34 , wherein N=32 and M=16 and wherein the first, second, and third source registers comprise 128-bit packed data registers. 
     
     
         38 . The method of  claim 34 , wherein the first plurality of packed real and imaginary data elements, and the third plurality of packed real and imaginary data elements, comprise complex data of input functions for an N×M Fast Fourier Transform (FFT) and wherein the second source register comprises real and imaginary data elements for a twiddle factor for the FFT. 
     
     
         39 . The method of  claim 38 , further comprising:
 sign-extending the first, second, third, and fourth selected real products or the first and second temporary results to a specified bit width.   
     
     
         40 . The method of  claim 39 , further comprising:
 sign-extending the first and second N-bit data elements from the third source register.   
     
     
         41 . The method of  claim 40 , further comprising:
 performing rounding and/or saturation of the pre-scaled results and/or the first, second, third, and fourth final results.   
     
     
         42 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations of:
 decoding a first instruction to generate a decoded instruction;   storing a first plurality of packed N-bit real and imaginary data elements in a first source register;   storing a second plurality of packed M-bit real and imaginary data elements in a second source register;   storing a third plurality of packed N-bit real and imaginary data elements in a third source register;   multiplying packed real N-bit data elements in the first source register with packed imaginary M-bit data elements in the second source register and multiplying packed imaginary N-bit data elements in the first source register with packed real M-bit data elements in the second source register to generate at least four imaginary products;   adding a first selected imaginary product and a second selected imaginary product to generate a first temporary result and to adding a third selected imaginary product and a fourth selected imaginary product to generate a second temporary result   adding the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, subtracting the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result;   scaling the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results; and   storing the first, second, third, and fourth final results in specified data element positions.   
     
     
         43 . The machine-readable medium of  claim 42 , wherein the scaling is performed in accordance with bit values in an immediate of the first instruction. 
     
     
         44 . The machine-readable medium of  claim 43 , wherein the immediate bit values comprise a first value to indicate no shifting, a second value to indicate a 1-bit shift, and a third value to indicate a 2-bit shift. 
     
     
         45 . The machine-readable medium of  claim 42 , wherein N=32 and M=16 and wherein the first, second, and third source registers comprise 128-bit packed data registers. 
     
     
         46 . The machine-readable medium of  claim 42 , wherein the first plurality of packed real and imaginary data elements, and the third plurality of packed real and imaginary data elements, comprise complex data of input functions for an N×M Fast Fourier Transform (FFT) and wherein the second source register comprises real and imaginary data elements for a twiddle factor for the FFT. 
     
     
         47 . The machine-readable medium of  claim 45 , further comprising program code to cause the machine to perform the operations of:
 sign-extending the first, second, third, and fourth selected real products or the first and second temporary results to a specified bit width.   
     
     
         48 . The machine-readable medium of  claim 47 , further comprising program code to cause the machine to perform the operations of:
 sign-extending the first and second N-bit data elements from the third source register.   
     
     
         49 . The machine-readable medium of  claim 48 , further comprising program code to cause the machine to perform the operations of:
 performing rounding and/or saturation of the pre-scaled results and/or the first, second, third, and fourth final results.   
     
     
         50 . An apparatus comprising:
 means for decoding a first instruction to generate a decoded instruction;   means for storing a first plurality of packed N-bit real and imaginary data elements in a first source register;   means for storing a second plurality of packed M-bit real and imaginary data elements in a second source register;   means for storing a third plurality of packed N-bit real and imaginary data elements in a third source register;   means for multiplying packed real N-bit data elements in the first source register with packed imaginary M-bit data elements in the second source register and multiplying packed imaginary N-bit data elements in the first source register with packed real M-bit data elements in the second source register to generate at least four imaginary products;   means for adding a first selected imaginary product and a second selected imaginary product to generate a first temporary result and to adding a third selected imaginary product and a fourth selected imaginary product to generate a second temporary result   means for adding the first temporary result to a first packed N-bit data element from the third source register to generate a first pre-scaled result, subtracting the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, adding the second temporary result to a second packed N-bit data element from the third source register to generate a third pre-scaled result, and subtracting the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result;   means for scaling the first, second, third and fourth pre-scaled results to a specified bit width to generate first, second, third, and fourth final results; and   means for storing the first, second, third, and fourth final results in specified data element positions.   
     
     
         51 . The apparatus of  claim 50 , wherein the scaling is performed in accordance with bit values in an immediate of the first instruction. 
     
     
         52 . The apparatus of  claim 51 , wherein the immediate bit values comprise a first value to indicate no shifting, a second value to indicate a 1-bit shift, and a third value to indicate a 2-bit shift. 
     
     
         53 . The apparatus of  claim 50 , wherein N=32 and M=16 and wherein the first, second, and third source registers comprise 128-bit packed data registers. 
     
     
         54 . The apparatus of  claim 50 , wherein the first plurality of packed real and imaginary data elements, and the third plurality of packed real and imaginary data elements, comprise complex data of input functions for an N×M Fast Fourier Transform (FFT) and wherein the second source register comprises real and imaginary data elements for a twiddle factor for the FFT. 
     
     
         55 . The apparatus of  claim 54 , further comprising:
 means for sign-extending the first, second, third, and fourth selected real products or the first and second temporary results to a specified bit width.   
     
     
         56 . The apparatus of  claim 55 , further comprising:
 means for sign-extending the first and second N-bit data elements from the third source register.   
     
     
         57 . The apparatus of  claim 56 , further comprising:
 means for performing rounding and/or saturation of the pre-scaled results and/or the first, second, third, and fourth final results.