Processor core energy management

Abstract

Methods and apparatus relating to techniques for processor core energy management are described. In an embodiment, energy management logic causes a modification to energy consumption by an electrical load (such as a processor core) based at least in part on comparison of an electrical current value and an operating current threshold value. The electrical current value is detected at an electrical current sensor coupled to the electrical load. Other embodiments are also disclosed and claimed.

1 . An apparatus comprising:
 a clock source to provide a clock to a core of a group of cores; and   a first power management unit to monitor current and to control the clock source to cause the clock source to increase a frequency of the clock based on monitored current, and without increasing a supply voltage for the core.   
     
     
         2 . The apparatus of  claim 1 , wherein the first power management unit causes the clock source to increase the frequency without increasing the supply voltage for the clock source, based on monitored current being less than a threshold current. 
     
     
         3 . The apparatus of  claim 1 , wherein each core of the core group has an associated voltage regulator to supply it with a core specific supply voltage. 
     
     
         4 . The apparatus of  claim 1 , wherein the second power management unit is coupled to the first power management unit via a control fabric. 
     
     
         5 . The apparatus of  claim 1 , wherein the core group is part of a first processor, the apparatus comprising a second processor having a second power management unit, wherein the first power management unit is communicatively coupled to the second power management unit via a fabric. 
     
     
         6 . The apparatus of  claim 5 , comprising circuitry to transfer information from a first clock domain of the core to a second clock domain of the first processor. The apparatus of  claim 1 , wherein the clock source comprises a PLL. 
     
     
         8 . The apparatus of claim  7 , wherein the PLL is to lock in at most  3  clock cycles. 
     
     
         9 . The apparatus of  claim 1 , wherein the clock source comprises a dynamic frequency scaling circuitry. 
     
     
         10 . An apparatus comprising:
 a sensor to monitor a current supplied to a processor having a core;   a clock source to increase frequency of a clock to the core when the monitored current is less than a threshold current, wherein the clock source is to reduce frequency of the clock to the core when the monitored current is above the threshold current; and   a first power management unit to control the clock source to increase the frequency of the clock to the core when the monitored current is less than the threshold current.   
     
     
         11 . The apparatus of  claim 10 , wherein the processor is a first processor and further comprising a second power management unit that is part of a second processor that is communicatively coupled to the first processor via a fabric. 
     
     
         12 . The apparatus of  claim 11 , comprising circuitry to transfer information from a first clock domain of the core to a second clock domain of the processor. 
     
     
         13 . The apparatus of  claim 11 , wherein the clock source is one of a PLL or a FLL. 
     
     
         14 . The apparatus of  claim 11 , wherein the temporarily increase frequency is performed at a constant power supply voltage level. 
     
     
         15 . The apparatus of  claim 11 , wherein each core has its own power plane. 
     
     
         16 . An apparatus comprising:
 a sensor circuitry to monitor a current supplied to a processor; and   a clock source to temporarily increase frequency of a clock to the processor based on the monitored current being less than a threshold current, wherein the clock source is to reduce frequency of the clock to the processor based on the monitored current being at or near the threshold current; and   a first power management unit to control the clock source to cause the clock source to temporarily increase the frequency of the clock to the processor based on the monitored current being less than the threshold current.   
     
     
         17 . The apparatus of  claim 16 , wherein the processor is a first processor, and wherein the apparatus further comprises a second processor and a second power management unit that is communicatively coupled to a first power management unit of the second processor via a fabric. 
     
     
         18 . The apparatus of  claim 16 , further comprising a second power management unit that is coupled to the core via a fabric. 
     
     
         19 . The apparatus of  claim 16 , comprising circuitry to transfer information from a first clock domain of the processor to a second clock domain of the processor. 
     
     
         20 . The apparatus of  claim 16 , wherein the temporarily increase in frequency is performed at a constant power supply voltage level.