Identifying and marking failed egress links in data plane

Abstract

A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.

1 - 15 . (canceled) 
     
     
         16 . An apparatus comprising:
 circuitry to receive packets, wherein the packets comprise header fields and wherein the packets are associated with a flow and stored in a queue;   ingress packet processing pipeline circuitry to:
 determine congestion associated with the queue, 
 process received packets to generate packet byte count information and packet count information, and 
 cause storage of the packet byte count information and packet count information; and 
   a traffic manager coupled to the ingress packet processing circuitry.   
     
     
         17 . The apparatus of  claim 16 , comprising an egress packet processing circuitry. 
     
     
         18 . The apparatus of  claim 17 , comprising one or more egress ports, wherein the egress packet processing circuitry is to select an egress port of the one or more egress ports for packet transmission based on a link aggregation group (LAG). 
     
     
         19 . The apparatus of  claim 16 , comprising one or more ingress ports and one or more egress ports. 
     
     
         20 . The apparatus of  claim 16 , comprising at least one port that is bi-directional for packet ingress and/or packet egress. 
     
     
         21 . The apparatus of  claim 16 , comprising at least one memory to store at least one of the received packets. 
     
     
         22 . The apparatus of  claim 16 , comprising a switch, wherein the switch comprises the circuitry to receive packets and the ingress packet processing pipeline circuitry. 
     
     
         23 . At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
 configure ingress packet processing pipeline circuitry of a switch to:
 determine congestion associated with a queue, 
 process received packets to generate packet byte count information and packet count information, and 
 cause storage of the packet byte count information and packet count information. 
   
     
     
         24 . The non-transitory computer-readable medium of  claim 23 , comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
 configure circuitry of a switch to
 receive packets and store received packets in a queue, wherein the packets comprise header fields and wherein the packets are associated with a flow. 
   
     
     
         25 . The non-transitory computer-readable medium of  claim 23 , comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
 configure egress packet processing circuitry of the switch to select an egress port of the one or more egress ports for packet transmission based on a link aggregation group (LAG).   
     
     
         26 . The non-transitory computer-readable medium of  claim 23 , wherein the switch comprises one or more ingress ports and one or more egress ports. 
     
     
         27 . The non-transitory computer-readable medium of  claim 23 , wherein the switch comprises at least one port that is bi-directional for packet ingress and/or packet egress. 
     
     
         28 . The non-transitory computer-readable medium of  claim 23 , wherein the switch comprises at least one memory to store at least one of the received packets. 
     
     
         29 . The non-transitory computer-readable medium of  claim 23 , wherein the switch comprises
 a traffic manager coupled to the ingress packet processing circuitry.   
     
     
         30 . A method comprising:
 storing received packets in a queue, wherein the packets comprise header fields and wherein the packets are associated with a flow;   ingress packet processing pipeline circuitry performing:
 determining congestion associated with the queue, 
 processing received packets to generate packet byte count information and packet count information, and 
 causing storage of the packet byte count information and packet count information. 
   
     
     
         31 . The method of  claim 30 , comprising:
 egress packet processing circuitry selecting an egress port for packet transmission based on a link aggregation group (LAG).   
     
     
         32 . The method of  claim 30 , comprising:
 performing traffic management of the received packets using a traffic manager.