Logic drive using standard commodity programmable logic ic chips

Abstract

A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

What is claimed is: 
     
         1 . A multi-chip package comprising:
 a component comprising a silicon substrate and an interconnection scheme over the silicon substrate, wherein the interconnection scheme comprises a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate and first interconnection metal layer, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers;   a non-volatile memory (NVM) integrated-circuit (IC) chip over and coupling to the component, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip comprises a memory cell for storing first data therein; and   a semiconductor integrated-circuit (IC) chip over and coupling to the component, wherein the semiconductor integrated-circuit (IC) chip comprises a static-random-access-memory (SRAM) cell for storing second data therein associated with the first data, and a selection circuit comprising a first set of input points for a first input data set and a second set of input points for a second input data set having data associated with the second data, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data at an output point of the selection circuit.   
     
     
         2 . The multi-chip package of  claim 1 , wherein the component comprises a through silicon via vertically in the silicon substrate. 
     
     
         3 . The multi-chip package of  claim 1 , wherein the component is an interposer. 
     
     
         4 . The multi-chip package of  claim 1  further comprising a plurality of tin-containing bumps under the component and at a bottom of the multi-chip package. 
     
     
         5 . The multi-chip package of  claim 1  further comprising a metal bump between the semiconductor integrated-circuit (IC) chip and component. 
     
     
         6 . The multi-chip package of  claim 5 , wherein the metal bump comprises tin. 
     
     
         7 . The multi-chip package of  claim 1 , wherein the non-volatile memory (NVM) integrated-circuit (IC) chip is a flash chip. 
     
     
         8 . The multi-chip package of  claim 1 , wherein the semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip. 
     
     
         9 . The multi-chip package of  claim 1 , wherein the second interconnection metal layer comprises a copper layer and an adhesion layer at a bottom of the copper layer but not at a sidewall of the copper layer. 
     
     
         10 . The multi-chip package of  claim 1 , wherein the first interconnection metal layer comprises a copper layer and an adhesion layer at a bottom and sidewall of the copper layer. 
     
     
         11 . The multi-chip package of  claim 1  further comprising a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over and coupling to the component, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip couples to the semiconductor integrated-circuit (IC) chip through the component. 
     
     
         12 . The multi-chip package of  claim 1  further comprising a central-processing-unit (CPU) chip over and coupling to the component, wherein the central-processing-unit (CPU) chip couples to the semiconductor integrated-circuit (IC) chip through the component. 
     
     
         13 . The multi-chip package of  claim 1  further comprising a graphic-processing-unit (GPU) chip over and coupling to the component, wherein the graphic-processing-unit (GPU) chip couples to the semiconductor integrated-circuit (IC) chip through the component. 
     
     
         14 . The multi-chip package of  claim 1  further comprising an input/output (I/O) chip over and coupling to the component, wherein the input/output (I/O) chip couples to the semiconductor integrated-circuit (IC) chip through the component. 
     
     
         15 . The multi-chip package of  claim 1  further comprising a dynamic-random-access-memory (DRAM) chip over and coupling to the component, wherein the dynamic-random-access-memory (DRAM) chip couples to the semiconductor integrated-circuit (IC) chip through the component. 
     
     
         16 . A multi-chip package comprising:
 a component comprising a silicon substrate and an interconnection scheme over the silicon substrate, wherein the interconnection scheme comprises a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate and first interconnection metal layer, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers;   a non-volatile memory (NVM) integrated-circuit (IC) chip over and coupling to the component, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip comprises a memory cell for storing first data therein; and   a semiconductor integrated-circuit (IC) chip over and coupling to the component, wherein the semiconductor integrated-circuit (IC) chip comprises a static-random-access-memory (SRAM) cell for storing second data therein associated with the first data, and a selection circuit comprising a first set of input points for a first input data set and a second set of input points for a second input data set having data associated with the second data, wherein the selection circuit is configured to select, in accordance with the second input data set, input data from the first input data set as output data at an output point of the selection circuit.   
     
     
         17 . The multi-chip package of  claim 16 , wherein the component comprises a through silicon via vertically in the silicon substrate. 
     
     
         18 . The multi-chip package of  claim 16  further comprising a plurality of tin-containing bumps under the component and at a bottom of the multi-chip package. 
     
     
         19 . The multi-chip package of  claim 16  further comprising a metal bump between the semiconductor integrated-circuit (IC) chip and component. 
     
     
         20 . The multi-chip package of  claim 19 , wherein the metal bump comprises tin. 
     
     
         21 . The multi-chip package of  claim 16 , wherein the semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip. 
     
     
         22 . The multi-chip package of  claim 16 , wherein the second interconnection metal layer comprises a copper layer and an adhesion layer at a bottom of the copper layer but not at a sidewall of the copper layer. 
     
     
         23 . The multi-chip package of  claim 16 , wherein the first interconnection metal layer comprises a copper layer and an adhesion layer at a bottom and sidewall of the copper layer. 
     
     
         24 . The multi-chip package of  claim 16  further comprising a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over and coupling to the component, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip couples to the semiconductor integrated-circuit (IC) chip through the component. 
     
     
         25 . The multi-chip package of  claim 16  further comprising a central-processing-unit (CPU) chip over and coupling to the component, wherein the central-processing-unit (CPU) chip couples to the semiconductor integrated-circuit (IC) chip through the component. 
     
     
         26 . The multi-chip package of  claim 16  further comprising an input/output (I/O) chip over and coupling to the component, wherein the input/output (I/O) chip couples to the semiconductor integrated-circuit (IC) chip through the component.