Design Method, Product and Application of High-Repetition-Frequency and Multi-Wavelength Ultrashort Pulse Mode-Locked Photonic Integrated Chip

Abstract

Disclosed are a design method, a product and an application of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip. Components for designing the mode-locked photonic integrated chip include a semiconductor optical amplifier array providing gains for N wavelength channels; a phase delay line array which includes phase delay lines with different lengths and separately compensates for different effective optical path differences of gain light of the wavelength channels caused by a dispersion effect; a flattened arrayed waveguide grating multiplexing the gain light with the effective optical path differences compensated, and multiplexing N-channel optical pulse signals into one-channel optical pulse signal; a saturable absorber forming, with the arrayed waveguide grating, N individual and synchronized different wavelength mode-locked optical pulse channels; and a semiconductor optical amplifier used for gaining and outputting an output pulse of the saturable absorber.

1 . A design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip, wherein components for designing the mode-locked photonic integrated chip comprise a semiconductor optical amplifier array, a phase delay line array, an arrayed waveguide grating, a saturable absorber and a semiconductor optical amplifier, adjacent components being connected through passive waveguides;
 wherein the semiconductor optical amplifier array separately provides gains for N different wavelength channels, N being an integer greater than or equal to 2;   the phase delay line array is identical to the semiconductor optical amplifier array in dimension, and the phase delay line array comprises phase delay lines which are made from passive waveguide materials and have different lengths, the phase delay lines with different lengths separately compensating for different effective optical path differences of gain light of the wavelength channels caused by a dispersion effect;   the arrayed waveguide grating is designed to be flattened and is used for multiplexing the gain light with the effective optical path differences compensated, and multiplexing N-channel optical pulse signals into one-channel optical pulse signal;   the saturable absorber is connected to an output end of the arrayed waveguide grating, and forms, with the arrayed waveguide grating, N individual and synchronized different wavelength mode-locked optical pulse channels; and   the semiconductor optical amplifier is used for gaining and outputting an output pulse of the saturable absorber.   
     
     
         2 . The design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 1 , wherein the saturable absorber is designed to be placed at 1/M position of a cavity length of the mode-locked photonic integrated chip, a forward current is applied to the semiconductor optical amplifier array and the semiconductor optical amplifier, and a reverse bias voltage is applied to the saturable absorber, so as to output an optical pulse with a high repetition frequency which is M times as high as a fundamental frequency. 
     
     
         3 . The design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 1 , wherein a multimode interferometer is designed on a waveguide incident plane of the arrayed waveguide grating to improve a transmission bandwidth of the arrayed waveguide grating. 
     
     
         4 . The design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 1 , wherein chirping of the output pulse is reduced by controlling a time-bandwidth product of the mode-locked photonic integrated chip to approach a transform limitation of a pulse mode. 
     
     
         5 . The design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 1 , wherein an external radio frequency (RF) source and a bias tee are added to the saturable absorber, and a reverse bias voltage applied to the saturable absorber and a RF clock signal are combined together by the bias tee, to be applied to the saturable absorber by a ground-signal probe, so as to realize hybrid mode locking. 
     
     
         6 . The design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 5 , wherein clock jitter of an optical pulse of the mode-locked photonic integrated chip is reduced by optimizing output power and an output frequency of the RF clock signal. 
     
     
         7 . The design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 6 , wherein the output power of the RF clock signal is greater than 20 dBm. 
     
     
         8 . A high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip, wherein it is obtained through the design method of a high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 1 . 
     
     
         9 . The high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 8 , wherein the saturable absorber is designed to be placed at 1/M position of a cavity length of the mode-locked photonic integrated chip, a forward current is applied to the semiconductor optical amplifier array and the semiconductor optical amplifier, and a reverse bias voltage is applied to the saturable absorber, so as to output an optical pulse with a high repetition frequency which is M times as high as a fundamental frequency. 
     
     
         10 . The high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 8 , wherein a multimode interferometer is designed on a waveguide incident plane of the arrayed waveguide grating to improve a transmission bandwidth of the arrayed waveguide grating. 
     
     
         11 . The high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 8 , wherein chirping of the output pulse is reduced by controlling a time-bandwidth product of the mode-locked photonic integrated chip to approach a transform limitation of a pulse mode. 
     
     
         12 . The high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 8 , wherein an external radio frequency (RF) source and a bias tee are added to the saturable absorber, and a reverse bias voltage applied to the saturable absorber and a RF clock signal are combined together by the bias tee, to be applied to the saturable absorber by a ground-signal probe, so as to realize hybrid mode locking. 
     
     
         13 . The high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 12 , wherein clock jitter of an optical pulse of the mode-locked photonic integrated chip is reduced by optimizing output power and an output frequency of the RF clock signal. 
     
     
         14 . A high-speed photonic analog-to-digital converter, comprising the high-repetition-frequency and multi-wavelength ultrashort pulse mode-locked photonic integrated chip according to  claim 6  as a light source.