Thin-film transistor structures with gas spacer

Abstract

An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

What is claimed is: 
     
         1 . An integrated circuit structure comprising:
 an array of transistor structures wherein adjacent transistor structures in the array are spaced by a gap of no more than 100 nm, and wherein at least some of the transistor structures include a body of semiconductor material, the body including a source region and a drain region;   a gate electrode vertically aligned with the body;   a gate dielectric between the gate electrode and the body;   a source electrode in contact with the source region; and a drain electrode in contact with the drain region;   isolation material on sidewalls of the transistor structures and at least partially encapsulating a gas pocket between adjacent transistor structures in the array;   word lines electrically coupled to the gate electrode of columns of the transistor structures in the array; and   bit lines electrically coupled to a source electrode and/or drain electrode of rows of the transistor structures in the array.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the isolation material encapsulates the gas pocket in the gap between at least 90% of adjacent transistor structures in a first direction of the array. 
     
     
         3 . The integrated circuit structure of  claim 1 , wherein the gas pocket has a volume of at least 10 nm 3 . 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein a vertical height of the transistor structures is from 50% to 150% of a horizontal distance of the gap. 
     
     
         5 . A method of fabricating an integrated circuit, the method comprising:
 forming a first transistor structure and a second transistor structure, the second transistor structure spaced from a first transistor structure by a gap no greater than 100 nm, wherein the first transistor structure and the second transistor structure each include a layer of semiconductor material, a layer of dielectric material, and a gate electrode vertically aligned with and spaced from the layer of semiconductor material by the layer of dielectric material; and   depositing a layer of insulator material in the gap, thereby encapsulating a gas pocket laterally between the first transistor structure and the second transistor structure.   
     
     
         6 . The method of  claim 5 , wherein depositing the layer of insulator material is performed at least in part by atomic layer deposition or physical vapor deposition. 
     
     
         7 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 an array of transistor structures wherein adjacent transistor structures in the array are spaced by a gap of no more than 100 nm, and wherein at least some of the transistor structures include a body of semiconductor material, the body including a source region and a drain region; 
 a gate electrode vertically aligned with the body; 
 a gate dielectric between the gate electrode and the body; 
 a source electrode in contact with the source region; and a drain electrode in contact with the drain region; 
 isolation material on sidewalls of the transistor structures and at least partially encapsulating a gas pocket between adjacent transistor structures in the array; 
 word lines electrically coupled to the gate electrode of columns of the transistor structures in the array; and 
 bit lines electrically coupled to a source electrode and/or drain electrode of rows of the transistor structures in the array. 
   
     
     
         8 . The computing device of  claim 7 , further comprising:
 a memory coupled to the board.   
     
     
         9 . The computing device of  claim 7 , further comprising:
 a communication chip coupled to the board.   
     
     
         10 . The computing device of  claim 7 , wherein the component is a packaged integrated circuit die. 
     
     
         11 . The computing device of  claim 7 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.