Semiconductor device and manufacturing method thereof

Abstract

A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first source/drain epitaxy structures over the semiconductor fin and on opposite sides of the first gate structure and forming second source/drain epitaxy structures over the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first source/drain epitaxy structures and bottom of the second source/drain epitaxy structures are lower than a top surface of the semiconductor fin; removing the third gate structure to expose the top surface of the semiconductor fin; forming an isolation structure in the semiconductor fin, wherein a bottom of the isolation structure is lower than the bottom of the first source/drain epitaxy structures and the bottom the second source/drain epitaxy structures.

What is claimed is: 
     
         1 . A method, comprising:
 forming a semiconductor fin over a substrate;   forming first, second, and third gate structures crossing the semiconductor fin;   forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure, and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure, wherein bottom of the first epitaxy structures and bottom of the second epitaxy structures are lower than a top surface of the semiconductor fin;   removing the third gate structure to form a recess in the semiconductor fin;   forming an isolation structure in the recess, wherein a bottom of the isolation structure is lower than the bottom of the first epitaxy structures and the bottom of the second epitaxy structures.   
     
     
         2 . The method of  claim 1 , wherein the isolation structure has a curved bottom from a cross-sectional view. 
     
     
         3 . The method of  claim 1 , further comprising forming shallow trench isolation structures laterally surrounding the semiconductor fin, wherein the bottom of the isolation structure is lower than top surfaces of the shallow trench isolation structures. 
     
     
         4 . The method of  claim 1 , further comprising forming an implantation region interfacing the bottom of the isolation structure. 
     
     
         5 . The method of  claim 1 , further comprising after forming the isolation structure, replacing the first and second gate structures with first and second metal gate structures, respectively. 
     
     
         6 . The method of  claim 1 , further comprising forming spacers on opposite sidewalls of the first, second, and third gate structures, wherein removing the third gate structure is performed to form a trench between a pair of the spacers, and the isolation structure is formed in contact with the pair of the spacers. 
     
     
         7 . The method of  claim 1 , wherein the isolation structure has a greater width variation below the top surface of the semiconductor fin than above the top surface of the semiconductor fin. 
     
     
         8 . The method of  claim 1 , wherein a width of the isolation structure above the top surface of the semiconductor fin is substantially equal to a width of the first and second gate structures. 
     
     
         9 . The method of  claim 1 , wherein the isolation structure is made of a single material. 
     
     
         10 . A method, comprising:
 forming a semiconductor fin over a substrate;   forming first, second, and third gate structures crossing the semiconductor fin;   forming first spacers on opposite sidewalls of the first gate structure, second spacers on opposite sidewalls of the second gate structure, and third spacers on opposite sidewalls of the third gate structure;   forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure;   removing the third gate structure to form a trench between the third spacers to expose a portion of the semiconductor fin;   etching the portion of the semiconductor fin exposed by the trench between the third spacers; and   forming a dielectric structure filling an entirety of the trench between the third spacers.   
     
     
         11 . The method of  claim 10 , further comprising after forming the dielectric structure, replacing the first and second gate structures with first and second metal gate structures, respectively. 
     
     
         12 . The method of  claim 10 , further comprising performing an implantation process to form an implantation region in a portion of the semiconductor fin directly below the trench between the third spacers. 
     
     
         13 . The method of  claim 12 , wherein the implantation region is lower than bottoms of the first and second epitaxy structures. 
     
     
         14 . The method of  claim 10 , further comprising performing a planarization process to the dielectric structure. 
     
     
         15 . A method, comprising:
 forming a semiconductor fin over a substrate;   forming first, second, and third gate structures crossing the semiconductor fin;   forming first epitaxy structures in the semiconductor fin and on opposite sides of the first gate structure and forming second epitaxy structures in the semiconductor fin and on opposite sides of the second gate structure;   removing the third gate structure to expose a portion of the semiconductor fin;   performing an implantation process to form an implantation region in the exposed portion of the semiconductor fin; and   forming a dielectric structure over the implantation region in the semiconductor fin.   
     
     
         16 . The method of  claim 15 , further comprising:
 after forming the dielectric structure, replacing the first gate structure with a first metal gate structure; and   after replacing the first gate structure with the first metal gate structure, replacing the second gate structure with a second metal gate structure, wherein the first and second gate structures have different compositions.   
     
     
         17 . The method of  claim 15 , further comprising forming first spacers on opposite sidewalls of the first gate structure, second spacers on opposite sidewalls of the second gate structure, and third spacers on opposite sidewalls of the third gate structure, wherein removing the third gate structure is performed to form a trench between the third spacers, and a widest width of the implantation region is substantially equal to a distance between the third spacers. 
     
     
         18 . The method of  claim 15 , wherein a bottom of the implantation region is higher than bottoms of the first and second epitaxy structures. 
     
     
         19 . The method of  claim 15 , wherein a height of the dielectric structure is substantially equal to heights of the first and second gate structures. 
     
     
         20 . The method of  claim 15 , wherein a top surface of the implantation region is level with a top surface of the semiconductor fin.