Ultrasound apparatuses and methods for fabricating ultrasound devices

Abstract

Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

What is claimed is: 
     
         1 . An ultrasound device, comprising:
 a plurality of micromachined ultrasonic transducers (MUT);   a first application-specific integrated circuit (ASIC) comprising:
 a pulser configured to provide a signal to a MUT of the plurality of MUTs; 
 integrated analog processing receive circuitry configured to process a signal produced by the MUT in response to receiving an acoustic signal; and 
 an analog-to-digital converter (ADC) configured to digitize a signal provided by the analog processing receive circuitry, and 
 serial-deserialized (SERDES) transmit circuitry, wherein the first ASIC is configured to operate at a first operating voltage and wherein the first ASIC is implemented in a first technology node; 
   a second ASIC comprising:
 SERDES receive circuitry and integrated digital processing circuitry configured to digitally process a signal provided by the SERDES receive circuitry, 
 wherein the integrated digital processing circuitry is configured to operate at a second operating voltage in a range of approximately 0.45-0.9 Volts, 
 wherein the first operating voltage is at least twenty-five times greater than the second operating voltage, and 
 wherein the second ASIC is implemented in a second technology node smaller than the first technology node; and 
   a conductive communication link coupling the SERDES transmit circuitry of the first ASIC and the SERDES receive circuitry of the second ASIC.   
     
     
         2 . The ultrasound device of  claim 1 , wherein the conductive communication link comprises a through-silicon via (TSV). 
     
     
         3 . The ultrasound device of  claim 1 , wherein the first technology node is 65 nm, 80 nm, 90 nm, 110 nm, 130 nm, 150 nm, 180 nm, 220 nm, 240 nm, 250 nm, 280 nm, 350 nm, or 500 nm. 
     
     
         4 . The ultrasound device of  claim 1 , wherein the second technology node is 90 nm, 80 nm, 65 nm, 55 nm, 45 nm, 40 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, or 3 nm. 
     
     
         5 . The ultrasound device of  claim 1 , wherein:
 the conductive communication link supports a data rate of approximately 2-5 gigabits/second.   
     
     
         6 . The ultrasound device of  claim 1 , wherein the conductive communication link is a first conductive communication link, and wherein the ultrasound device comprises multiple conducive communication links operating in parallel and coupling the SERDES transmit circuitry of the first ASIC and the SERDES receive circuitry of the second ASIC. 
     
     
         7 . The ultrasound device of  claim 1 , wherein:
 the analog-to-digital converter (ADC) is one of multiple ADCs; and   the SERDES transmit circuitry is configured to transmit, to the second ASIC, data generated by the multiple ADCs in a multiplexed fashion.   
     
     
         8 . The ultrasound device of  claim 1 , wherein the ADC of the first ASIC is disposed electrically between the integrated analog processing receive circuitry and the SERDES transmit circuitry of the first ASIC. 
     
     
         9 . The ultrasound device of  claim 1 , further comprising a printed circuit board (PCB), wherein:
 the conductive communication link comprises a trace of the PCB, and   the SERDES receive circuitry of the second ASIC is disposed between the trace of the PCB and the integrated digital processing circuitry of the second ASIC.   
     
     
         10 . The ultrasound device of  claim 1 , further comprising a printed circuit board (PCB), wherein the first and second ASICs are both coupled to the PCB. 
     
     
         11 . The ultrasound device of  claim 1 , wherein the first ASIC is disposed electrically between the plurality of MUTs and the second ASIC. 
     
     
         12 . The ultrasound device of  claim 1 , wherein the second ASIC is bonded to the first ASIC via thermocompression bonding, eutectic bonding, silicide bonding or solder bonding. 
     
     
         13 . The ultrasound device of  claim 1 , wherein the integrated analog processing receive circuitry comprises an analog amplifier, an analog filter, analog beamforming circuitry, analog dechirp circuitry, analog quadrature demodulation (AQDM) circuitry, analog time delay circuitry, analog phase shifter circuitry, analog summing circuitry, analog time gain compensation circuitry, and/or analog averaging circuitry. 
     
     
         14 . The ultrasound device of  claim 1 , wherein the integrated digital processing circuitry comprises one or more digital filters, digital beamforming circuitry, digital quadrature demodulation (DQDM) circuitry, averaging circuitry, digital dechirp circuitry, digital time delay circuitry, digital phase shifter circuitry, digital summing circuitry, digital multiplying circuitry, requantization circuitry, waveform removal circuitry, formation circuitry, backend processing circuitry and/or one or more output buffers. 
     
     
         15 . The ultrasound device of  claim 1 , wherein the pulser comprises a multi-level pulser. 
     
     
         16 . The ultrasound device of  claim 1 , the ADC comprises a delta-sigma ADC. 
     
     
         17 . The ultrasound device of  claim 16 , wherein the delta-sigma ADC lacks current integrators. 
     
     
         18 . The ultrasound device of  claim 1 , wherein the plurality of MUTs comprise capacitive MUTs (CMUTs). 
     
     
         19 . The ultrasound device of  claim 1 , wherein the plurality of CMUTs are formed on a substrate bonded to the first ASIC. 
     
     
         20 . The ultrasound device of  claim 1 , wherein the first operating voltage is in a range of approximately 5-30 Volts or in a range of approximately 30-80 Volts.