Memory device including a ferroelectric semiconductor channel and methods of forming the same

Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a gate dielectric and a ferroelectric semiconductor channel layer that is laterally spaced from the electrically conductive layers by the gate dielectric.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 an alternating stack of insulating layers and electrically conductive layers located over a substrate;   a memory opening vertically extending through the alternating stack; and   a memory opening fill structure located within the memory opening, wherein the memory opening fill structure comprises a gate dielectric, a ferroelectric semiconductor channel layer that is laterally spaced from the electrically conductive layers by the gate dielectric.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the ferroelectric semiconductor channel layer comprises an indium selenide material. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the indium selenide material has a rhombohedral R3m crystalline structure and has a material composition of In 2 Se 3+δ , wherein δ is in a range from 0.3 to 0.5. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the ferroelectric semiconductor channel layer has a lateral thickness of 1 to 10 atomic monolayers. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the ferroelectric semiconductor channel layer has a lateral thickness in a range from 0.65 nm to 10 nm. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the ferroelectric semiconductor channel layer has a tubular configuration with a uniform thickness between an inner sidewall and an outer sidewall. 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising a drain region contacting a top end of the ferroelectric semiconductor channel layer, wherein the drain region comprises a material selected from a doped elemental semiconductor material, a doped compound semiconductor material, a stack including a titanium layer and a gold layer, a stack including a nickel layer and a gold layer, or a metal silicide material. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein cylindrical sidewalls of the electrically conductive layers are in direct contact with an outer sidewall of the gate dielectric. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein an inner sidewall of the gate dielectric contacts an outer sidewall of the ferroelectric semiconductor channel layer. 
     
     
         10 . The semiconductor structure of  claim 1 , further comprising an outer interfacial dielectric layer contacting an inner sidewall of the gate dielectric and an outer sidewall of the ferroelectric semiconductor channel layer. 
     
     
         11 . The semiconductor structure of  claim 1 , further comprising a dielectric core laterally surrounded by and contacting an inner sidewall of the ferroelectric semiconductor channel layer. 
     
     
         12 . The semiconductor structure of  claim 1 , further comprising:
 an inner interfacial dielectric layer contacting an inner sidewall of the ferroelectric semiconductor channel layer; and   a dielectric core laterally surrounded by and contacting an inner sidewall of the inner interfacial dielectric layer.   
     
     
         13 . The semiconductor structure of  claim 1 , wherein:
 the substrate comprises a semiconductor material layer; and   the memory opening fill structure comprises a pedestal channel portion in contact with the semiconductor material layer, in contact with a bottom surface of the gate dielectric, in contact with a bottom surface of the ferroelectric semiconductor channel layer, and laterally surrounded by a bottommost electrically conductive layer among the electrically conductive layers.   
     
     
         14 . The semiconductor structure of  claim 1 , wherein the substrate comprises a source contact layer in contact with an outer sidewall of the ferroelectric semiconductor channel layer. 
     
     
         15 . The semiconductor structure of  claim 1 , further comprising:
 additional memory openings vertically extending through the alternating stack; and   additional memory opening fill structures located within the memory openings, wherein the semiconductor structure comprises a three-dimensional memory array including a two-dimensional array of ferroelectric semiconductor channel layers located within the additional memory opening fill structures.   
     
     
         16 . A method of forming a semiconductor structure, comprising:
 forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;   forming a memory opening through the alternating stack; and   forming a memory opening fill structure within the memory opening, by sequentially forming a gate dielectric and a ferroelectric semiconductor channel layer that is laterally spaced from the electrically conductive layers by the gate dielectric.   
     
     
         17 . The method of  claim 16 , wherein the ferroelectric semiconductor channel layer comprises an indium selenide material. 
     
     
         18 . The method of  claim 17 , wherein the indium selenide material has a rhombohedral R3m crystalline structure and has a material composition of In 2 Se 3+δ , wherein δ is in a range from 0.3 to 0.5. 
     
     
         19 . The method of  claim 16 , wherein:
 the ferroelectric semiconductor channel layer has a charge carrier mobility in range from 100 cm 2 /(V·s) to 2,000 cm 2 /(V·s); and   the ferroelectric semiconductor channel layer has a lateral thickness in a range from 0.65 nm to 10 nm.   
     
     
         20 . The method of  claim 16 , further comprising forming a drain region contacting a top end of the ferroelectric semiconductor channel layer, wherein the drain region comprises a material selected from a doped elemental semiconductor material, a doped compound semiconductor material, a stack including a titanium layer and a gold layer, a stack including a nickel layer and a gold layer, or a metal silicide material.