Plane spanning data redundancy in solid state storage devices

Abstract

Data redundancy arrangements for memory and storage devices are discussed herein. In one example, a method of operating a data storage system includes writing data to a non-volatile memory die by at least spanning bits of the data and one or more data redundancy bits generated for the data across a quantity of data storage cells of more than one plane of the non-volatile memory die. The more than one plane of the non-volatile memory die comprise groupings of data storage cells having independent source lines and bit lines that provide for concurrent write operations to the more than one plane.

What is claimed is: 
     
         1 . A method, comprising:
 writing data to a non-volatile memory die by at least spanning bits of the data and one or more data redundancy bits generated for the data across a quantity of data storage cells of more than one plane of the non-volatile memory die; and   wherein the more than one plane of the non-volatile memory die comprise groupings of data storage cells having independent source lines and bit lines that provide for concurrent write operations to the more than one plane.   
     
     
         2 . The method of  claim 1 , comprising:
 generating the one or more data redundancy bits generated for the data.   
     
     
         3 . The method of  claim 1 , wherein the one or more data redundancy bits comprise XOR bits calculated from the bits of the data. 
     
     
         4 . The method of  claim 1 , wherein the one or more data redundancy bits are written subsequent to the bits of the data. 
     
     
         5 . The method of  claim 1 , comprising:
 spanning the bits of the data over the more than one plane of the non-volatile memory die and storing the one or more data redundancy bits in memory cells on a single plane of the non-volatile memory die.   
     
     
         6 . The method of  claim 1 , wherein the data storage cells comprise multi-level cells; and comprising:
 writing the bits of the data as first multi-level representations into first memory cells; and   writing the one or more data redundancy bits as second multi-level representations into second memory cells.   
     
     
         7 . The method of  claim 1 , wherein the non-volatile memory die comprises a 3D NAND flash memory die. 
     
     
         8 . A storage control system, comprising:
 a memory interface configured to write data to a non-volatile memory die by at least spanning bits of the data and one or more data redundancy bits generated for the data across a quantity of data storage cells of more than one plane of the non-volatile memory die; and   wherein the more than one plane of the non-volatile memory die comprise groupings of data storage cells having independent source lines and bit lines that provide for concurrent write operations to the more than one plane.   
     
     
         9 . The storage control system of  claim 8 , comprising:
 a data interface configured to obtain the data for storage; and   control circuitry configured to generate the one or more data redundancy bits.   
     
     
         10 . The storage control system of  claim 8 , wherein the one or more data redundancy bits comprise XOR bits calculated from the bits of the data. 
     
     
         11 . The storage control system of  claim 8 , wherein the one or more data redundancy bits are written subsequent to the data. 
     
     
         12 . The storage control system of  claim 8 , comprising:
 the memory interface configured to span the bits of the data over the more than one plane of the non-volatile memory die and store the one or more data redundancy bits in memory cells on a single plane of the non-volatile memory die.   
     
     
         13 . The storage control system of  claim 8 , wherein the data storage cells comprise multi-level cells; and comprising:
 the memory interface configured to write the bits of the data as first multi-level representations into first memory cells, and write the one or more data redundancy bits as second multi-level representations into second memory cells.   
     
     
         14 . The storage control system of  claim 8 , wherein the non-volatile memory die comprises a 3D NAND flash memory die. 
     
     
         15 . An apparatus, comprising:
 one or more computer readable storage media;   program instructions stored on the one or more computer readable storage media, the program instructions executable by a processing system to direct the processing system to at least:   control a write process to write data to a non-volatile memory die by at least spanning bits of the data and one or more data redundancy bits generated for the data across a quantity of data storage cells of more than one plane of the non-volatile memory die; and   wherein the more than one plane of the non-volatile memory die comprise groupings of data storage cells having independent source lines and bit lines that provide for concurrent write operations to the more than one plane.   
     
     
         16 . The apparatus of  claim 15 , comprising further instructions executable by the processing system to direct the processing system to at least:
 generate the one or more data redundancy bits for the data.   
     
     
         17 . The apparatus of  claim 15 , wherein the one or more data redundancy bits comprise XOR bits calculated from the bits of the data. 
     
     
         18 . The apparatus of  claim 15 , comprising further instructions executable by the processing system to direct the processing system to at least:
 control the write process to write the data to the non-volatile memory die by at least spanning the bits of the data over the more than one plane of the non-volatile memory die and storing the one or more data redundancy bits in memory cells on a single plane of the non-volatile memory die.   
     
     
         19 . The apparatus of  claim 15 , wherein the data storage cells comprise multi-level cells; and comprising further instructions executable by the processing system to direct the processing system to at least:
 control the write process to write the one or more data pages to the non-volatile memory die by at least writing the bits of the data as first multi-level representations into first memory cells, and writing the one or more data redundancy bits as second multi-level representations into second memory cells.   
     
     
         20 . The apparatus of  claim 15 , wherein the non-volatile memory die comprises a 3D NAND flash memory die.