Counter based multiply-and-accumulate circuit for neural network

Abstract

Disclosed herein includes a system, a method, and a device for improving computation efficiency of a neural network. In one aspect, adder circuitry is configured to add input data from processing of the neural network and a first number of bits of accumulated data for the neural network to generate summation data. In one aspect, according to a carry value of the adding from the adder circuitry, a multiplexer is configured to select between i) a second number of bits of the accumulated data and ii) incremented data comprising the second number of bits of the accumulated data incremented by a predetermined value. The summation data appended with the selected one of the second number of bits of the accumulated data or the incremented data may form appended data.

What is claimed is: 
     
         1 . A circuit comprising:
 adder circuitry configured to generate summation data having a first number of bits for a first clock cycle by adding input data having the first number of bits and a first portion of a first accumulated data having the first number of bits for the first clock cycle, the adder circuitry including a carry port to generate a carry value of the summation data; and   a multiplexer including a control port coupled to the carry port, the multiplexer configured to generate a selected data, according to the carry value at the control port, the selected data selected from either i) a second portion of the first accumulated data having a second number of bits, or ii) a sum of the second portion of the first accumulated data and the carry value, the summation data having the first number of bits appended with the selected data having the second number of bits being a second accumulated data for a second clock cycle.   
     
     
         2 . The circuit of  claim 1 , wherein the multiplexer is configured to select the second portion of the first accumulated data as the selected data, in response to the carry value being zero. 
     
     
         3 . The circuit of  claim 1 , wherein the multiplexer is configured to select the sum as the selected data, in response to the carry value being one. 
     
     
         4 . The circuit of  claim 1 , wherein the adder circuitry includes:
 output ports to provide the summation data having the first number of bits, and   input ports coupled to the output ports of the adder circuitry, the input ports to receive the summation data as a first portion of the second accumulated data for the second clock cycle.   
     
     
         5 . The circuit of  claim 1 , further comprising:
 incrementing circuitry including output ports coupled to first input ports of the multiplexer, the incrementing circuitry configured to add the second portion of the first accumulated data and the carry value to generate the sum at the output ports of the incrementing circuitry.   
     
     
         6 . The circuit of  claim 5 , wherein the multiplexer includes output ports coupled to i) input ports of the incrementing circuitry and ii) second input ports of the multiplexer. 
     
     
         7 . The circuit of  claim 1 , further comprising:
 multiplier circuitry including output ports coupled to input ports of the adder circuitry, the multiplier circuitry configured to multiply first data and second data to generate the input data at the output ports of the multiplier circuitry.   
     
     
         8 . The circuit of  claim 7 , wherein the first data is weight of a neural network and the second data is an activation value of the neural network. 
     
     
         9 . The circuit of  claim 8 , wherein the first data has a third number of bits, and the second data has the third number of bits, the first number being twice of the third number. 
     
     
         10 . A method comprising:
 generating, by adder circuitry, summation data having a first number of bits for a first clock cycle by adding input data having the first number of bits and a first portion of a first accumulated data having the first number of bits for the first clock cycle, the adder circuitry including a carry port to generate a carry value of the summation data; and   generating, by a multiplexer, a selected data by selecting, according to the carry value at a control port coupled to the carry port of the adder circuitry, either i) a second portion of the first accumulated data having a second number of bits, or ii) a sum of the second portion of the first accumulated data and the carry value, the summation data having the first number of bits appended with the selected data having the second number of bits being a second accumulated data for a second clock cycle.   
     
     
         11 . The method of  claim 10 , further comprising:
 selecting, by the multiplexer, the second portion of the first accumulated data as the selected data, in response to the carry value being zero.   
     
     
         12 . The method of  claim 10 , further comprising:
 selecting, by the multiplexer, the sum as the selected data, in response to the carry value being one.   
     
     
         13 . The method of  claim 10 , further comprising:
 providing, by the adder circuitry, the summation data having the first number of bits at output ports of the adder circuitry; and   receiving, by the adder circuitry, the summation data as a first portion of the second accumulated data for the second clock cycle at input ports of the adder circuitry coupled to the output ports of the adder circuitry.   
     
     
         14 . The method of  claim 10 , further comprising:
 adding, by incrementing circuitry including output ports coupled to first input ports of the multiplexer, the second portion of the first accumulated data and the carry value to generate the sum at the output ports of the incrementing circuitry.   
     
     
         15 . The method of  claim 14 , wherein the multiplexer includes output ports coupled to i) input ports of the incrementing circuitry and ii) second input ports of the multiplexer. 
     
     
         16 . The method of  claim 10 , further comprising:
 multiplying, by multiplier circuitry including output ports coupled to input ports of the adder circuitry, first data and second data to generate the input data at the output ports of the multiplier circuitry.   
     
     
         17 . The method of  claim 16 , wherein the first data is weight of a neural network and the second data is an activation value of the neural network. 
     
     
         18 . The method of  claim 17 , wherein the first data has a third number of bits, and the second data has the third number of bits, the first number being twice of the third number. 
     
     
         19 . A device comprising:
 adder circuitry configured to add input data having a first number of bits and a first portion of a first accumulated data having the first number of bits to obtain a first output data for a first clock cycle;   incrementing circuitry configured to increment a second portion of the first accumulated data having a second number of bits by a predetermined value to obtain a second output data for the first clock cycle; and   a multiplexer configured to generate a selected data, according to a carry value of the adding by the adder circuitry, the selected data selected from either i) the second output data output from the incrementing circuitry during the first clock cycle, or ii) a third output data output from the multiplexer during a second clock cycle before the first clock cycle.   
     
     
         20 . The device of  claim 19 , wherein the first output data output from the adder circuitry appended with the selected data from the multiplexer forms a second accumulated data.