Memory structure with doping-induced leakage paths

Abstract

The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

What is claimed is: 
     
         1 . A method, comprising:
 receiving a workpiece comprising:
 a dielectric layer, 
 a first contact feature disposed in the dielectric layer, and 
 a second contact feature disposed in the dielectric layer and adjacent the first contact feature; 
   after receiving the workpiece, reducing a breakdown voltage of the dielectric layer; and   applying a programming voltage across the first contact feature and the second contact feature to break down the dielectric layer between the first contact feature and the second contact feature,   wherein the programming voltage is equal to or greater than the breakdown voltage of the dielectric layer.   
     
     
         2 . The method of  claim 1 , wherein the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG). 
     
     
         3 . The method of  claim 1 ,
 wherein the first contact feature is disposed over and in electrical communication with a gate structure,   wherein the second contact feature is disposed over and in electrical communication with a source/drain feature.   
     
     
         4 . The method of  claim 3 ,
 wherein the gate structure comprises a gate dielectric layer,   wherein a breakdown voltage of the gate dielectric layer is greater than the breakdown voltage of the dielectric layer between the first contact feature and the second contact feature.   
     
     
         5 . The method of  claim 4 ,
 wherein the gate dielectric layer comprises hafnium oxide,   wherein the breakdown voltage of the gate dielectric layer is between about 4.5 volts and about 5.5 volts.   
     
     
         6 . The method of  claim 1 , wherein the reducing of the breakdown voltage comprises performing an implantation process on the dielectric layer to introduce defects and impurities in the dielectric layer. 
     
     
         7 . The method of  claim 6 , wherein the implantation process implants a group  4 A element. 
     
     
         8 . The method of  claim 6 , wherein the implantation process implants germanium (Ge) or tin (Sn). 
     
     
         9 . The method of  claim 8 , wherein the implantation process comprises an implantation dose between about 5×10 14  atoms/cm 2  and about 1×10 15  atoms/cm 2 . 
     
     
         10 . The method of  claim 8 , wherein the implantation process comprises an ion implantation energy between about 5 keV and about 30 keV. 
     
     
         11 . A semiconductor device, comprising:
 an active region;   a gate structure over a channel region of the active region;   a gate spacer disposed along a sidewall of the gate structure;   a source/drain feature over a source/drain region of the active region;   a dielectric layer disposed over the gate structure and the source/drain feature;   a gate contact disposed in the dielectric layer and directly over the gate structure;   a source/drain contact disposed in the dielectric layer and directly over the source/drain feature; and   a leakage feature bridging between and electrically coupling the gate contact and the source/drain contact,   wherein the leakage feature is spaced apart from the gate spacer by a portion of the dielectric layer.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the leakage feature comprises copper (Cu), aluminum (Al), tungsten (W), ruthenium (Ru), nickel (Ni), cobalt (Co), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), nickel nitride (NiN), or cobalt nitride (CoN). 
     
     
         13 . The semiconductor device of  claim 11 , wherein the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG). 
     
     
         14 . The semiconductor device of  claim 11 , wherein the dielectric layer is doped with germanium (Ge) or tin (Sn). 
     
     
         15 . The semiconductor device of  claim 11 ,
 wherein the gate structure comprises a gate dielectric layer disposed on the channel region of the active region,   wherein the gate dielectric layer has a breakdown between about 4.5 volts and about 5.5 volts.   
     
     
         16 . The semiconductor device of  claim 11 , wherein the active region comprises a fin structure. 
     
     
         17 . A one-time programmable (OTP) memory device, comprising:
 a fin structure;   a gate structure disposed over a channel region of the fin structure;   a source/drain feature disposed over a source/drain region of the fin structure;   a dielectric layer disposed over the gate structure and the source/drain feature;   a gate contact disposed in the dielectric layer and electrically coupled to the gate structure; and   a source/drain contact disposed in the dielectric layer and electrically coupled to the source/drain feature,   wherein the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG),   wherein the dielectric layer is doped with germanium (Ge) or tin (Sn) such that a portion of the dielectric layer between the gate contact and the source/drain contact has a breakdown voltage between about 2 volts and about 3 volts.   
     
     
         18 . The OTP memory device of  claim 17 ,
 wherein the gate structure comprises a gate dielectric layer wrapping over the fin structure and a gate electrode over the gate dielectric layer,   wherein the gate dielectric layer has a breakdown voltage between about 4.5 volts and about 5.5 volts.   
     
     
         19 . The OTP memory device of  claim 17 , wherein the gate structure and the source/drain contact are spaced apart by a gate spacer and the contact etch stop layer (CESL). 
     
     
         20 . The OTP memory device of  claim 19 ,
 wherein the gate spacer comprises silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, or silicon oxycarbonitride,   wherein the CESL comprises silicon nitride, silicon oxide, or silicon oxynitride.