US2022293540A1PendingUtilityA1

Semiconductor structure and method of fabricating the same

Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Jan 16, 2020Filed: May 30, 2022Published: Sep 15, 2022
Est. expiryJan 16, 2040(~13.5 yrs left)· nominal 20-yr term from priority
H10W 99/00H10W 80/00H10W 90/288H10W 90/28H10W 90/297H10W 72/823H10W 72/01H10W 72/0198H10W 72/874H10W 72/853H10W 72/9445H10W 72/952H10W 72/932H10W 72/9413H10W 72/01953H10W 72/01955H10W 72/01935H10W 72/01938H10W 90/00H10W 70/09H10W 72/941H10W 72/951H10W 70/60H10W 90/22H10W 72/241H10W 90/792H10W 72/963H10W 72/965H10W 72/967H10W 90/732H10W 90/26H10W 80/327H10W 80/312H10W 72/07331H10W 72/942H10W 72/923H10W 72/877H10W 72/242H10W 72/29H10W 74/111H10W 72/30H10W 72/019H10W 72/013H10W 40/22H10W 20/42H10W 74/117H10W 74/01H10W 70/05H10W 20/43H10W 40/228H10W 70/65H01L 25/50H01L 2225/06565H01L 2224/83895H01L 24/27H01L 24/03H01L 23/3107H01L 2224/08147H01L 24/73H01L 23/5226H01L 23/528H01L 2224/13023H01L 2224/06519H01L 24/13H01L 2224/32145H01L 23/367H01L 24/32H01L 2224/80895H01L 24/83H01L 2224/0401H01L 25/0657H01L 2224/73253H01L 2224/83896H01L 24/06H01L 24/05H01L 24/29H01L 24/08H01L 2224/05025H01L 2225/06541H01L 2224/80896
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Claims

Abstract

A semiconductor structure including a semiconductor substrate, an interconnect structure disposed over the semiconductor substrate, and a bonding structure disposed over the interconnect structure is provided. The bonding structure includes a dielectric layer covering the interconnect structure, signal transmission features penetrating through the dielectric layer, and a thermal conductive feature penetrating through the dielectric layer. The thermal conductive feature includes a thermal routing and thermal pads, and the thermal pads are disposed on and share the thermal routing.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a semiconductor substrate;   an interconnect structure disposed over the semiconductor substrate, the interconnect structure comprising interconnect wirings, a passivation layer covering the interconnect wirings and a first thermal conductor partially covered by the passivation layer; and   a bonding structure disposed over the interconnect structure, the bonding structure comprising a dielectric layer covering the interconnect structure, signal transmission features penetrating through the dielectric layer, and a thermal conductive feature penetrating through the dielectric layer, wherein the thermal conductive feature is in contact with the first thermal conductor.   
     
     
         2 . The semiconductor structure as claimed in  claim 1 , wherein the dielectric layer comprises a bonding dielectric layer and an inter-dielectric layer disposed between the bonding dielectric layer and the interconnect structure. 
     
     
         3 . The semiconductor structure as claimed in  claim 2 , wherein each signal transmission feature among the signal transmission features comprises a via penetrating through the inter-dielectric layer and a bonding pad penetrating through the bonding dielectric layer, and the bonding pad is electrically connected to the interconnect structure through the via. 
     
     
         4 . The semiconductor structure as claimed in  claim 2 , wherein the thermal conductive feature comprises a thermal routing and thermal pads, the thermal pads are disposed on and share the thermal routing, the thermal routing laterally extends between at least two neighboring signal transmission features among the signal transmission features, the thermal routing penetrates through the inter-dielectric layer, and the thermal pads penetrate through the bonding dielectric layer. 
     
     
         5 . The semiconductor structure as claimed in  claim 2 , wherein the bonding structure further comprises dummy pads embedded in the bonding dielectric layer, and the dummy pads are electrically insulated from the interconnect structure by the inter-dielectric layer. 
     
     
         6 . The semiconductor structure as claimed in  claim 1 , wherein the thermal conductive feature comprises a thermal routing and thermal pads, the thermal pads are disposed on and share the thermal routing, the thermal routing laterally extends between at least two neighboring signal transmission features among the signal transmission features, and the thermal routing laterally extends along a meandering path. 
     
     
         7 . The semiconductor structure as claimed in  claim 1 , wherein the thermal conductive feature comprises a thermal routing and thermal pads, the thermal pads are disposed on and share the thermal routing, the thermal routing laterally extends between at least two neighboring signal transmission features among the signal transmission features, the thermal routing comprises via portions and wall portions laterally connecting via portions, and the via portions are in contact with the thermal pads, and wherein at least one of the wall portions laterally extend between at least two neighboring signal transmission features among the signal transmission features. 
     
     
         8 . The semiconductor structure as claimed in  claim 1 , wherein the thermal conductive feature is electrically insulated from the signal transmission features. 
     
     
         9 . The semiconductor structure as claimed in  claim 1 , wherein the thermal conductive feature is electrical floating. 
     
     
         10 . The semiconductor structure as claimed in  claim 1 , wherein the thermal conductive feature comprises a thermal routing and thermal pads, the thermal pads are disposed on and share the thermal routing, the thermal routing laterally extends between at least two neighboring signal transmission features among the signal transmission features, the interconnect structure further comprises a second thermal conductor disposed over the passivation layer, and a second portion of the thermal routing is landed on the second thermal conductor. 
     
     
         11 . A semiconductor structure, comprising:
 a first semiconductor die comprising an interconnect structure and a first bonding structure, the interconnect structure comprising interconnect wirings, a passivation layer covering the interconnect wirings and a thermal conductor partially covered by the passivation layer, and the thermal routing being in contact with the thermal conductor, the first bonding structure comprising a first dielectric layer, first signal transmission features penetrating through the first dielectric layer, and a first thermal conductive feature penetrating through the first dielectric layer;   a second semiconductor die comprising a second bonding structure, the second bonding structure comprising a second dielectric layer, second signal transmission features penetrating through the second dielectric layer, and a second thermal conductive feature penetrating through the second dielectric layer; and   an insulating encapsulant disposed on the second semiconductor die and encapsulating the first semiconductor die,   wherein the first dielectric layer is bonded to the second dielectric layer, the first signal transmission features are bonded and electrically connected to the second signal transmission features, and the first thermal pads are bonded and thermally coupled to the second thermal pads.   
     
     
         12 . The semiconductor structure as claimed in  claim 11 , wherein the first thermal conductive feature comprises a first thermal routing and first thermal pads, the first thermal pads are disposed on and share the first thermal routing, and the first thermal routing laterally extends between at least two neighboring first signal transmission features among the first signal transmission features, and the first thermal routing comprises a meshed thermal routing. 
     
     
         13 . The semiconductor structure as claimed in  claim 11 , wherein the first thermal conductive feature and the second thermal conductive feature are electrical floating, and the first thermal conductive feature and the second thermal conductive feature are electrically insulated from the first signal transmission features and the second signal transmission features. 
     
     
         14 . The semiconductor structure as claimed in  claim 11 , wherein the first bonding structure further comprises first dummy pads embedded in the first dielectric layer, the second bonding structure further comprises second dummy pads embedded in the second dielectric layer, the first dummy pads and the second dummy pads are bonded. 
     
     
         15 . The semiconductor structure as claimed in  claim 11 , wherein the first thermal conductive feature comprises a first thermal routing and first thermal pads, the first thermal pads are disposed on and share the first thermal routing, and the first thermal routing laterally extends between at least two neighboring first signal transmission features among the first signal transmission features, the first thermal routing comprises first via portions and first wall portions laterally connecting first via portions, and the first via portions are in contact with the first thermal pads, and wherein at least one of the first wall portions laterally extend between at least two neighboring first signal transmission features among the first signal transmission features. 
     
     
         16 . The semiconductor structure as claimed in  claim 11 , wherein the second thermal conductive feature comprises a second thermal routing and second thermal pads, and the second thermal pads are disposed on and share the second thermal routing, the second thermal routing comprises second via portions and second wall portions laterally connecting second via portions, and the second via portions are in contact with the second thermal pads, and wherein at least one of the second wall portions laterally extend between at least two neighboring second signal transmission features among the second signal transmission features. 
     
     
         17 . A method, comprising:
 providing a semiconductor substrate having an interconnect structure disposed thereon, wherein the interconnect structure comprises interconnect wirings, a passivation layer covering the interconnect wirings and a thermal conductor partially covered by the passivation layer; and   forming an inter-dielectric layer over the interconnect structure;   forming vias and a thermal routing in the inter-dielectric layer, wherein and the thermal routing is in contact with the thermal conductor;   forming a bonding dielectric layer over the inter-dielectric layer; and   forming bonding pads and thermal pads in the bonding dielectric layer, wherein the bonding pads are formed on the vias.   
     
     
         18 . The method as claimed in  claim 17 , wherein dummy pads are in the bonding dielectric layer when forming the bonding pads and the thermal pads in the bonding dielectric layer, and the dummy pads are electrically insulated from the interconnect structure by the inter-dielectric layer. 
     
     
         19 . The method as claimed in  claim 17 , wherein the thermal routing is formed on a thermal conductor partially covered by the passivation layer of the interconnect structure. 
     
     
         20 . The method as claimed in  claim 17 , wherein the thermal routing is formed on a thermal conductor disposed over the passivation layer of the interconnect structure, and the thermal conductor is embedded in the inter-dielectric layer.

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