Memory controller and method of operating the same

Abstract

The present technology relates to an electronic device. More specifically, the present technology relates to a memory controller and a method of operating the same. According to an embodiment, a memory controller includes an error corrector configured to receive read data from a memory device and output a first message obtained by performing error correction decoding on the read data based on a parity check matrix, a randomizer configured to generate a second message by inverting the first message, and an operation controller configured to output the second message, wherein the parity check matrix is a matrix in which a number of elements, each of which is one (1) among elements included in each row, is an even number or a matrix in which an exclusive OR on elements included in each row is zero (0).

What is claimed is: 
     
         1 . A memory controller comprising:
 an error corrector configured to receive read data from a memory device and output a first message obtained by performing error correction decoding on the read data based on a parity check matrix;   a randomizer configured to generate a second message by inverting the first message; and   an operation controller configured to output the second message,   wherein the parity check matrix is a matrix in which a number of elements, each of which is one (1) among elements included in each row, is an even number or a matrix in which an exclusive OR on elements included in each row is zero (0).   
     
     
         2 . The memory controller of  claim 1 , wherein the read data is a codeword obtained by performing error correction encoding on write data provided from a host by the error corrector, and then inverting by the randomizer. 
     
     
         3 . The memory controller of  claim 1 , wherein the read data is a codeword obtained by inverting write data provided from a host by the randomizer, and then performing error correction encoding by the error corrector. 
     
     
         4 . The memory controller of  claim 1 , wherein the parity check matrix is the matrix in which the number of elements, each of which is one (1) among the elements included in each row, is the even number when the error correction decoding of the read data is performed based on a binary low density parity check (LDPC) code. 
     
     
         5 . The memory controller of  claim 1 , wherein the parity check matrix is the matrix in which the exclusive OR on the elements included in each row is zero (0) when the error correction decoding of the read data is performed based on a non-binary LDPC code. 
     
     
         6 . The memory controller of  claim 1 , wherein the randomizer generates the second message by inverting all bits included in the first message. 
     
     
         7 . A method of operating a memory controller, the method comprising:
 generating an inverted codeword according to a preset one of a first policy and a second policy based on write data to be stored in a memory device and a generator matrix, in response to a write request of a host;   providing the inverted codeword to the memory device;   receiving the inverted codeword from the memory device in response to a read request of the host;   performing error correction decoding on the inverted codeword based on a parity check matrix to generate a first message;   inverting the first message to generate a second message; and   providing the second message to the host,   wherein the parity check matrix is a matrix in which a number of elements, each of which is one (1) among elements included in each row, is an even number or a matrix in which an exclusive OR on elements included in each row is zero (0).   
     
     
         8 . The method of  claim 7 , wherein the generating of the inverted codeword comprises:
 performing error correction encoding on the write data according to the first policy to generate a codeword; and   inverting the codeword to generate the inverted codeword.   
     
     
         9 . The method of  claim 7 , wherein the generating of the inverted codeword comprises:
 inverting the write data according to the second policy to generate inverted write data; and   performing error correction encoding on the inverted write data to generate the inverted codeword.   
     
     
         10 . The method of  claim 7 , wherein the inverting of the first message comprises inverting all bits included in the first message. 
     
     
         11 . The method of  claim 7 ,
 wherein the parity check matrix is the matrix in which the number of elements, each of which is one (1) among the elements included in each row, is the even number when the error correction decoding is performed based on a binary low density parity check (LDPC) code, and   wherein the parity check matrix is the matrix in which the exclusive OR on the elements included in each row is zero (0) when the error correction decoding is performed based on a non-binary LDPC code.   
     
     
         12 . The method of  claim 7 , further comprising determining whether the error correction decoding is successful after the performing of the error correction decoding. 
     
     
         13 . The method of  claim 12 , wherein the first message is inverted when the error correction decoding is successful. 
     
     
         14 . The method of  claim 12 , further comprising providing a read fail signal to the host in response to failure of the error correction decoding. 
     
     
         15 . An operating method of a controller, the operating method comprising:
 error-correction-decoding on a codeword, which is read out from a memory device, based on a parity check matrix to generate a message; and   bitwise-inverting the message to provide a host with the bitwise-inverted message,   wherein the parity check matrix includes one or more rows each having even number of ones (1s) or one or more rows, each having elements, on which exclusive OR results in zero (0), and   wherein the generator matrix and the parity check matrix have a relationship as follows:   GH T =0, where ‘G’ represents the generator matrix and ‘HT’ represents a transpose matrix of the parity check matrix.   
     
     
         16 . The operating method of  claim 15 , wherein the codeword is data that is error-correction-encoded based on a generator matrix and then bitwise-inverted when stored into the memory device. 
     
     
         17 . The operating method of  claim 15 , wherein the codeword is data that is bitwise-inverted and then error-correction-encoded based on a generator matrix when stored into the memory device.