Pulse output circuit, display device, and electronic device

Abstract

An object of the present invention is to suppress deterioration in the thin film transistor. A plurality of pulse output circuits each include first to eleventh thin film transistors is formed. The pulse output circuit is operated on the basis of a plurality of clock signals which control each transistor, the previous stage signal input from a pulse output circuit in the previous stage, the next stage signal input from a pulse output circuit in the next stage, and a reset signal. In addition, a microcrystalline semiconductor is used for a semiconductor layer serving as a channel region of each transistor. Therefore, degradation of characteristics of the transistor can be suppressed.

1 . (canceled) 
     
     
         2 . A display device comprising:
 a shift register comprising:
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; 
 a seventh transistor; 
 an eighth transistor; and 
 a capacitor, 
   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,   wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor through the eighth transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the second transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor,   wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,   wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring,   wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor,   wherein the other of the source and the drain of the eighth transistor is electrically connected to the one of the source and the drain of the third transistor,   wherein a gate of the eighth transistor is electrically connected to a third wiring,   wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,   wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor, and   wherein a second electrode of the capacitor is electrically connected to the second wiring.   
     
     
         3 . The display device according to  claim 2 ,
 wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor.   
     
     
         4 . A display device comprising:
 a shift register comprising:
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; 
 a seventh transistor; 
 an eighth transistor; and 
 a capacitor, 
   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,   wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor through the eighth transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the second transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor,   wherein the other of the source and the drain of the first transistor is electrically connected to a signal line,   wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line,   wherein the other of the source and the drain of the fourth transistor is electrically connected to the first power supply line,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the first power supply line,   wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor,   wherein the other of the source and the drain of the eighth transistor is electrically connected to the one of the source and the drain of the third transistor,   wherein a gate of the eighth transistor is electrically connected to a second power supply line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to the second power supply line,   wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor, and   wherein a second electrode of the capacitor is electrically connected to the first power supply line.   
     
     
         5 . The display device according to  claim 4 ,
 wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor.   
     
     
         6 . A display device comprising:
 a shift register comprising:
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; 
 a seventh transistor; 
 an eighth transistor; 
 a ninth transistor; 
 a tenth transistor; 
 an eleventh transistor; 
 a twelfth transistor; 
 a thirteenth transistor; 
 a fourteenth transistor; 
 a fifteenth transistor; 
 a sixteenth transistor; 
 a first capacitor; and 
 a second capacitor, 
   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,   wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor through the eighth transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the seventh transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the second transistor,   wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor,   wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,   wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring,   wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor,   wherein the other of the source and the drain of the eighth transistor is electrically connected to the one of the source and the drain of the third transistor,   wherein a gate of the eighth transistor is electrically connected to a third wiring,   wherein the other of the source and the drain of the fifth transistor is electrically connected to the third wiring,   wherein a first electrode of the first capacitor is electrically connected to the gate of the second transistor,   wherein a second electrode of the first capacitor is electrically connected to the second wiring,   wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,   wherein one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor,   wherein the one of the source and the drain of the eleventh transistor is electrically connected to a gate of the ninth transistor through the sixteenth transistor,   wherein one of a source and a drain of the thirteenth transistor is electrically connected to one of a source and a drain of the fourteenth transistor,   wherein the one of the source and the drain of the thirteenth transistor is electrically connected to one of a source and a drain of the fifteenth transistor,   wherein the one of the source and the drain of the thirteenth transistor is electrically connected to a gate of the tenth transistor,   wherein the one of the source and the drain of the thirteenth transistor is electrically connected to a gate of the twelfth transistor,   wherein the other of the source and the drain of the ninth transistor is electrically connected to a fourth wiring,   wherein the other of the source and the drain of the tenth transistor is electrically connected to the second wiring,   wherein the other of the source and the drain of the twelfth transistor is electrically connected to the second wiring,   wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the second wiring,   wherein one of a source and a drain of the sixteenth transistor is electrically connected to the gate of the ninth transistor,   wherein the other of the source and the drain of the sixteenth transistor is electrically connected to the one of the source and the drain of the eleventh transistor,   wherein a gate of the sixteenth transistor is electrically connected to the third wiring,   wherein the other of the source and the drain of the thirteenth transistor is electrically connected to the third wiring,   wherein a first electrode of the second capacitor is electrically connected to the gate of the tenth transistor,   wherein a second electrode of the second capacitor is electrically connected to the second wiring, and   wherein the one of the source and the drain of the first transistor is electrically connected to a gate of the eleventh transistor.   
     
     
         7 . The display device according to  claim 6 ,
 wherein a gate of the third transistor is electrically connected to a gate of the sixth transistor.