Semiconductor devices with liners and related methods

Abstract

Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.

What is claimed is: 
     
         1 . A semiconductor device comprising an array of memory cells, at least one memory cell of the array of memory cells comprising:
 a control gate electrically isolated from an underlying charge structure by a dielectric material;   another dielectric material underlying the charge structure and overlying a material; and   a liner directly on sidewalls of the control gate and directly on sidewalls and an upper surface of a capping region over the control gate, the liner comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride, the liner not on sidewalls of the charge structure, and a thickness of the liner on the sidewalls of the capping region greater than a thickness of the liner on the sidewalls of the control gate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the control gate comprises a single material. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the capping region comprises multiple dielectric materials. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the control gate and the capping region comprise substantially continuous smooth sidewalls. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the liner comprises a densified material comprising hydrogen-occupied bonds. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the control gate comprises tungsten and the liner comprises silicon oxide. 
     
     
         7 . A method of forming a semiconductor device comprising an array of memory cells, the method comprising:
 forming control gate regions over a stack of materials, the control gate regions comprising a metallic material;   forming capping regions over the control gate regions;   forming a liner material comprising hydrogen and at least one of an oxide, a nitride, or an oxynitride directly on sidewalls of the control gate regions and sidewalls and an upper surface of the capping region, the liner material extending substantially continuously over the control gate regions and the capping regions;   exposing the liner material to a radical oxidation treatment to form a densified liner; and   patterning the stack of materials to form the array of memory cells without patterning the control gate regions and the capping regions, the memory cells spaced from adjacent memory cells by trenches.   
     
     
         8 . The method of  claim 7 , wherein, after patterning the base stack of materials, a thickness of the densified liner on the sidewalls of the control gate regions is less than a thickness of the densified liner on the sidewalls of the capping regions. 
     
     
         9 . The method of  claim 7 , wherein forming capping regions over the control gate regions comprises forming the sidewalls of the capping regions to be substantially horizontally aligned with the sidewalls of the control gate regions. 
     
     
         10 . The method of  claim 7 , wherein patterning the base stack of materials comprises:
 forming charge block regions underlying the control gate regions;   forming charge structures underlying the charge block regions; and   forming tunnel dielectric regions underlying the charge block regions,   wherein a width of each of the charge block regions, a width of each of the charge structures, and a width of each of the tunnel dielectric regions is greater than a width of the control gate regions.   
     
     
         11 . The method of  claim 7 , wherein patterning the base stack of materials comprises using the densified liner as a masking material to pattern the base stack of materials. 
     
     
         12 . The method of  claim 7 , wherein exposing the liner material to a radical oxidation treatment to form a densified liner comprises forming the densified liner having a thickness substantially the same as a thickness of the liner material. 
     
     
         13 . The method of  claim 7 , wherein exposing the liner material to a radical oxidation treatment to form a densified liner comprises forming the densified liner having a thickness greater than a thickness of the liner material. 
     
     
         14 . The method of  claim 7 , wherein exposing the liner material to a radical oxidation treatment comprises exposing the liner material to the radical oxidation treatment at a radical-forming temperature for a period of time within a range of from about 2 seconds to about 5 minutes. 
     
     
         15 . The method of  claim 7 , wherein forming control gate regions over a stack of materials comprises forming the control gate regions over the stack of materials comprising:
 a substrate;   a tunnel dielectric material overlying the substrate;   a charge structure material overlying the tunnel dielectric material; and   a charge blocking region overlying the charge structure material,   wherein the trenches extend vertically through the stack of materials and at least partially into the substrate.   
     
     
         16 . A semiconductor device comprising:
 memory cells, at least one memory cell of the memory cells comprising:
 a control gate region overlying a charge structure; 
 a capping region overlying the control gate region; 
 a liner directly contacting the capping region and directly contacting the sidewalls of the control gate region, the liner not directly contacting sidewalls of the charge structure. 
   
     
     
         17 . The semiconductor device of  claim 16 , wherein the sidewalls of the control gate region and sidewalls of the capping region comprise substantially continuous vertical surfaces. 
     
     
         18 . The semiconductor device of  claim 16 , wherein sidewalls of the charge structure are sloped relative to the sidewalls of the control gate region and sidewalls of the capping region. 
     
     
         19 . The semiconductor device of  claim 16 , wherein the liner extends substantially continuously over the capping region and the sidewalls of the control gate region. 
     
     
         20 . The semiconductor device of  claim 16 , wherein an entire upper surface of the control gate region is in direct contact with an entire lower surface of the capping region.