Configurable logic platform with reconfigurable processing circuitry

Abstract

A configurable logic platform may include a physical interconnect for connecting to a processing system, first and second reconfigurable logic regions, a configuration port for applying configuration data to the first and second reconfigurable logic regions, and a reconfiguration logic function accessible via transactions of the physical interconnect, the reconfiguration logic function providing restricted access to the configuration port from the physical interconnect. The platform may include a first interface function providing an interface to the first reconfigurable logic region and a second interface function providing an interface to the first reconfigurable logic region. The first and second interface functions may allow information to be transmitted over the physical interconnect and prevent the respective reconfigurable logic region from directly accessing the physical interconnect. The platform may include logic configured to apportion bandwidth of the physical interconnect among the interface functions.

1 . (canceled) 
     
     
         2 . A data processing system, comprising:
 a first manycore processor unit that includes a first processing unit configured to execute a hosted functionality, a first programmable logic component, and a first local link configured to couple the first processing unit with the first programmable logic component;   a second manycore processor unit that includes a second processing unit, a second programmable logic component, and a second local link configured to couple the second processing unit with the second programmable logic component; and   a mapping component provided on the first manycore processor unit, the second manycore processor unit, or a third manycore processor unit in the data processing system, the mapping component being configured to, in different instances, cause different processing tasks requested by the hosted functionality on the first processing unit to be satisfied by the first processing unit, the first programmable logic component, the second processing unit, and the second programmable logic component,   the mapping component being further configured to,
 in a particular instance, cause a particular processing task requested on the first processing unit to be performed locally on the first programmable logic component based at least on a mapping consideration, and 
 in another instance, reconfigure the second programmable logic component to perform another processing task responsive to another determination that the second programmable logic component is not already configured to perform the another processing task. 
   
     
     
         3 . The data processing system of  claim 2 , wherein the first processing unit and the second processing unit are central processing units configured to execute program instructions. 
     
     
         4 . The data processing system of  claim 2 , wherein the mapping component is configured to, in a further instance, cause the first programmable logic component to perform a further processing task based at least on a further determination that the first programmable logic component is already configured to provide the further processing task. 
     
     
         5 . The data processing system of  claim 2 , wherein the mapping component is configured to, in a further instance, select the first programmable logic component or the second programmable logic component to perform a further processing task based at least on a contractual entitlement associated with the further processing task. 
     
     
         6 . The data processing system of  claim 2 , wherein the first programmable logic component and the second programmable logic component comprise field-programmable gate arrays. 
     
     
         7 . The data processing system of  claim 6 , wherein the mapping component is further configured to, in a further instance, instruct the first processing unit to perform a further processing task on behalf of an individual instance of hosted functionality executing on the first processing unit. 
     
     
         8 . A method comprising:
 receiving requests to execute different processing tasks in a data processing system comprising a first manycore processor unit and a second manycore processor unit, the first manycore processor unit having a first processing unit and a first programmable logic component, the second manycore processor unit having a second processing unit and a second programmable logic component;   causing the different processing tasks to be performed in different instances on the first processing unit and the first programmable logic component of the first manycore processor unit and on the second processing unit and the second programmable logic component of the second manycore processor unit;   in a particular instance, causing a particular processing task to be performed locally on the first programmable logic component based at least on a mapping consideration; and   in another instance, reconfiguring the second programmable logic component to perform another processing task responsive to another determination that the second programmable logic component is not already configured to perform the another processing task, and causing the second programmable logic component to perform the another processing task after being reconfigured.   
     
     
         9 . The method of  claim 8 , wherein the first processing unit and the second processing unit are central processing units configured to execute program instructions. 
     
     
         10 . The method of  claim 8 , wherein the mapping consideration relates to the first programmable logic component being already configured to provide the further processing task. 
     
     
         11 . The method of  claim 8 , wherein the mapping consideration comprises contractual entitlement associated with the particular processing task. 
     
     
         12 . The method of  claim 8 , wherein the first programmable logic component and the second programmable logic component comprise field-programmable gate arrays. 
     
     
         13 . A system comprising:
 a first manycore processor unit that includes a first processing unit configured to execute hosted functionality that requests processing tasks, a first programmable logic component, and a first local link configured to couple the first processing unit with the first programmable logic component;   a second manycore processor unit that includes a second processing unit, a second programmable logic component, and a second local link configured to couple the second processing unit with the second programmable logic component;   a third manycore processor unit that includes a third processing unit; and   a common network shared by the first processing unit, the first programmable logic component, the second processing unit, the second programmable logic component, and the third processing unit, the third processing unit being configured to
 cause different processing tasks to be performed in different instances on the first processing unit and the first programmable logic component of the first manycore processor unit and on the second processing unit and the second programmable logic component of the second manycore processor unit, 
 in a particular instance, cause a particular processing task requested on the first manycore processor unit to be performed locally on the first programmable logic component based at least on a characteristic of the particular processing task, and 
 in another instance, reconfigure the second programmable logic component to perform another processing task responsive to another determination that the second programmable logic component is not already configured to perform the another processing task, and cause the second programmable logic component to perform the another processing task after being reconfigured. 
   
     
     
         14 . The system of  claim 13 , wherein the first processing unit and the second processing unit are central processing units configured to execute program instructions. 
     
     
         15 . The system of  claim 13 , wherein the first programmable logic component and the second programmable logic component comprise field-programmable gate arrays.