Transistor devices having source/drain structure configured with high germanium content portion

Abstract

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

1 . An integrated circuit device, comprising:
 a semiconductor fin comprising at least one of silicon and germanium;   a gate structure around the semiconductor fin, the gate structure including a gate electrode and a gate dielectric between the semiconductor fin and the gate electrode;   a source structure or drain structure adjacent the semiconductor fin, the source structure or drain structure including a first portion and a second portion, the first portion comprising at least one of silicon and germanium, and the second portion comprising a p-type dopant and germanium, the second portion having a germanium concentration in excess of 80 atomic %, wherein the first portion is thinner than the second portion, and wherein the first portion is between the second portion and the semiconductor fin; and   a contact structure on the second portion of the source structure or drain structure.   
     
     
         2 . The device of  claim 1 , wherein the semiconductor fin consists essentially of silicon, and the first portion of the source structure or drain structure consists essentially of silicon or silicon and germanium. 
     
     
         3 . The device of  claim 1 , wherein the semiconductor fin consists essentially of germanium, and the first portion of the source structure or drain structure consists essentially of silicon or silicon and germanium. 
     
     
         4 . The device of  claim 1 , wherein the semiconductor fin consists essentially of silicon and germanium, and the first portion of the source structure or drain structure consists essentially of silicon or silicon and germanium. 
     
     
         5 . The device of  claim 1 , wherein gate structure is on three sides of the semiconductor fin. 
     
     
         6 . The device of  claim 1 , wherein the second portion further comprises tin, the tin concentration being in the range of 3 atomic % to 8 atomic %. 
     
     
         7 . A computing device, comprising: a board; and
 a component coupled to the board, the component including an integrated circuit structure, comprising:   a semiconductor fin comprising at least one of silicon and germanium;   a gate structure around the semiconductor fin, the gate structure including a gate electrode and a gate dielectric between the semiconductor fin and the gate electrode;   a source structure or drain structure adjacent the semiconductor fin, the source structure or drain structure including a first portion and a second portion, the first portion comprising at least one of silicon and germanium, and the second portion comprising a p-type dopant and germanium, the second portion having a germanium concentration in excess of 80 atomic %, wherein the first portion is thinner than the second portion, and wherein the first portion is between the second portion and the semiconductor fin; and   a contact structure on the second portion of the source structure or drain structure.   
     
     
         8 . The computing device of  claim 7 , further comprising: a memory coupled to the board. 
     
     
         9 . The computing device of  claim 7 , further comprising: a communication chip coupled to the board. 
     
     
         10 . The computing device of  claim 7 , wherein the component is a packaged integrated circuit die.