Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a bottom die, a top die bonded to the bottom die, an insulating layer disposed on the bottom die and laterally covering the top die, a first dual-damascene connector overlying the insulating layer and the top die. The bottom die is wider than the top die, and a bonding interface of the top and bottom dies is substantially flat. The first dual-damascene connector is inserted into the insulating layer to be in electrical and physical contact with the bottom die.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a bottom die;   a top die bonded to the bottom die, the bottom die being wider than the top die, and a bonding interface of the top and bottom dies being substantially flat;   an insulating layer disposed on the bottom die and laterally covering the top die; and   a first dual-damascene connector overlying the insulating layer and the top die, and the first dual-damascene connector inserted into the insulating layer to be in electrical and physical contact with the bottom die.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein an inner sidewall of the insulating layer covering the first dual-damascene connector comprises a surface roughness greater than a surface roughness of the bonding interface. 
     
     
         3 . The semiconductor structure of  claim 1 , further comprising:
 a second dual-damascene connector comprising a pad portion overlying the top die and a via portion inserted into the top die.   
     
     
         4 . The semiconductor structure of  claim 3 , wherein the second dual-damascene connector comprises:
 a conductive liner layer lining with an inner sidewall of a semiconductor substrate of the top die, a rear surface of the semiconductor substrate connected to the inner sidewall of the semiconductor substrate; and   a conductive material layer overlying the conductive liner layer.   
     
     
         5 . The semiconductor structure of  claim 3 , wherein a surface roughness of the inner sidewall of the semiconductor substrate of the top die is greater than that of an interconnect circuitry of the top die underlying the semiconductor substrate. 
     
     
         6 . The semiconductor structure of  claim 3 , further comprising:
 an isolating liner interposed between the semiconductor substrate of the top die and the second dual-damascene connector.   
     
     
         7 . The semiconductor structure of  claim 3 , further comprising:
 a dielectric layer disposed on the insulating layer and the top die to laterally cover a pad portion of the first dual-damascene connector and the pad portion of the second dual-damascene connector, wherein the dielectric layer and the insulating layer are of different materials.   
     
     
         8 . A semiconductor structure, comprising:
 a bottom die;   a top die stacked upon and fused to the bottom die;   an insulating layer disposed on the bottom die and laterally covering the top die;   a first die connector comprising a first via portion laterally covered by the insulating layer and landing on the bottom die; and   a second die connector comprising a second via portion inserted into the top die.   
     
     
         9 . The semiconductor structure of  claim 8 , wherein a surface roughness of an inner sidewall of the insulating layer surrounding the first via portion of the first die connector is greater than that of a bonding surface of the bottom die. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein the second via portion of the second die connector extends through a semiconductor substrate of the top die and lands on an interconnect circuitry of the top die underlying the semiconductor substrate. 
     
     
         11 . The semiconductor structure of  claim 10 , further comprising:
 an isolating liner interposed between the semiconductor substrate of the top die and the second die connector.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein the isolating liner covers a surface of the semiconductor substrate of the top die that has a surface roughness greater than a surface roughness of the bonding surface of the bottom die. 
     
     
         13 . The semiconductor structure of  claim 8 , wherein the second die connector comprises:
 a conductive material layer; and   a conductive liner layer lining with a via opening of the top die and extending over a rear surface of the top die opposite to the bottom die, and the conductive liner layer interposed between the conductive material layer and the top die.   
     
     
         14 . The semiconductor structure of  claim 8 , further comprising:
 a polymer layer disposed on the insulating layer and the top die, the polymer layer separating a pad portion of the first die connector from a pad portion of the second die connector, and a surface roughness of an inner sidewall of the polymer layer being greater than a surface roughness of a bonding surface of the bottom die.   
     
     
         15 . A semiconductor structure, comprising:
 a bottom die;   a top die bonded to the bottom die, the bottom die being wider than the top die, and a bonding interface of the top and bottom dies being substantially flat;   an insulating layer disposed on the bottom die and laterally covering the top die, a surface roughness of an inner sidewall of the insulating layer being greater than that of the bonding interface; and   a first dual-damascene connector comprising a via portion surrounded by the inner sidewall of the insulating layer and landing on the bottom die.   
     
     
         16 . The semiconductor structure of  claim 15 , further comprising:
 a second dual-damascene connector comprising a via portion inserted into the top die.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein the via portion of the second dual-damascene connector passing through a semiconductor substrate of the top die and lands on an interconnect circuitry of the top die underlying the semiconductor substrate. 
     
     
         18 . The semiconductor structure of  claim 17 , wherein a surface roughness of an inner sidewall of the semiconductor substrate of the top die surrounding the via portion of the second dual-damascene connector is greater than that of the bonding interface. 
     
     
         19 . The semiconductor structure of  claim 15 , wherein the bonding interface comprises metal-to-metal bonds and dielectric-to-dielectric bonds. 
     
     
         20 . The semiconductor structure of  claim 15 , wherein the first dual-damascene connector further comprises a pad portion connected to the via portion and overlying the insulating layer and the top die.