Superjunction Transistor Device

Abstract

A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: first regions of a first doping type and second regions of a second doping type in an inner region and an edge region of a semiconductor body; and transistor cells each having a body region and a source region in the inner region of the semiconductor body. An effective lateral doping dose of the first regions in the edge region is lower than an effective lateral doping dose of the first regions in the inner region. An effective lateral doping dose of the second regions in the edge region is lower than an effective lateral doping dose of the second regions in the inner region.

What is claimed is: 
     
         1 . A transistor device, comprising:
 a plurality of first regions of a first doping type and a plurality of second regions of a second doping type in an inner region and an edge region of a semiconductor body; and   a plurality of transistor cells each comprising a body region and a source region in the inner region of the semiconductor body,   wherein an effective lateral doping dose of the first regions in the edge region is lower than an effective lateral doping dose of the first regions in the inner region,   wherein an effective lateral doping dose of the second regions in the edge region is lower than an effective lateral doping dose of the second regions in the inner region.   
     
     
         2 . The transistor device of  claim 1 , wherein in a first region and an adjoining second region in the inner region and in a first region and an adjoining second region in the edge region, the overall amount of first type dopant atoms is the same and the overall amount of second type dopant atoms is the same. 
     
     
         3 . The transistor device of  claim 1 , wherein in each transistor cell, the source region is separated from a first region by the body region. 
     
     
         4 . The transistor device of  claim 1 , wherein in each transistor cell, a second region adjoins the body region. 
     
     
         5 . The transistor device of  claim 1 , wherein each transistor cell comprises a drain region that adjoins a first region and a second region. 
     
     
         6 . The transistor device of  claim 1 , wherein each transistor cell comprises a drain region and a buffer region of the first doping type, the buffer region arranged between the drain region and each of a first region and a second region. 
     
     
         7 . The transistor device of  claim 1 , wherein first regions of two neighboring transistor cells are formed by one contiguous semiconductor region of the first doping type, and wherein second regions of two other transistor cells are formed by a contiguous semiconductor region of the second doping type. 
     
     
         8 . The transistor device of  claim 1 , wherein each transistor cell comprises a gate electrode that is arranged adjacent to the body region and that is dielectrically insulated from the body region by a gate dielectric. 
     
     
         9 . The transistor device of  claim 8 , wherein the source region and the body region of the individual transistor cells are connected to a source electrode that is electrically insulated from the gate electrodes by an insulation layer. 
     
     
         10 . The transistor device of  claim 1 , wherein in the inner region, each of the first and second regions adjoins at least one body region, and wherein in the edge region, a majority of the first and second regions do not adjoin a body region. 
     
     
         11 . The transistor device of  claim 1 , wherein at most an innermost one of the first and second regions located in the edge region adjoins a body region of a transistor cell. 
     
     
         12 . The transistor device of  claim 1 , wherein the first regions and the second regions are arranged alternatingly in a first horizontal of the semiconductor body and elongated in a second horizontal direction, and wherein the second horizontal direction is perpendicular to the first horizontal direction. 
     
     
         13 . The transistor device of  claim 1 , wherein some of the first regions are entirely arranged in the edge region while others of the first regions have sections in the inner region and sections in the edge region, and wherein some of the second regions are entirely arranged in the edge region while others of the second regions have sections in the inner region and sections in the edge region. 
     
     
         14 . The transistor device of  claim 1 , wherein the effective lateral doping doses of the first regions and the second region vary in a vertical direction. 
     
     
         15 . The transistor device of  claim 1 , wherein there is at least one vertical position of the semiconductor body at which at least some of the first regions located in the edge region are more lowly doped than the first regions located in the inner region, and wherein there is at least one vertical position of the semiconductor body at which at least some of the second regions located in the edge region are more lowly doped than the second regions located in the inner region. 
     
     
         16 . The transistor device of  claim 1 , wherein the lateral doping dose of a first region at a vertical position is dependent on a dimension of the first region in a lateral dimension and the effective doping concentration of the first doping type. 
     
     
         17 . The transistor device of  claim 16 , wherein the effective doping concentration of the first doping type varies in the lateral direction. 
     
     
         18 . The transistor device of  claim 1 , wherein the lateral doping dose of a second region at a vertical position is dependent on a dimension of the second region in a lateral dimension and the effective doping concentration of the second doping type. 
     
     
         19 . The transistor device of  claim 18 , wherein the effective doping concentration of the second doping type varies in the lateral direction. 
     
     
         20 . The transistor device of  claim 1 , wherein the transistor device is implemented as a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or as an IGBT (Insulated Gate Bipolar Transistor).