Multi-bit memory system with adaptive read voltage controller

Abstract

According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

1 - 18 . (canceled) 
     
     
         19 . A memory system comprising:
 a semiconductor memory including a first word line, a first plurality of memory cells coupled to the first word line, a second word line, and a second plurality of memory cells coupled to the second word line, each of the first plurality of memory cells being capable of storing a plurality of bits, each of the second plurality of memory cells being capable of storing a plurality of bits, a first memory cell of the first plurality of memory cells and a second memory cell of the second plurality of memory cells being connected in series; and   a controller configured to control the semiconductor memory, wherein   the semiconductor memory is configured to apply a first voltage within a first range to the first word line to read a first data from the first plurality of memory cells, apply a second voltage within the first range to the first word line to read a second data from the first plurality of memory cells, apply a third voltage within the first range to the first word line to read a third data from the first plurality of memory cells, and apply a fourth voltage within the first range to the first word line to read a fourth data from the first plurality of memory cells,   the second voltage is higher than the first voltage,   the third voltage is higher than the second voltage,   the fourth voltage is higher than the third voltage,   the controller is configured to determine a fifth voltage based on the first data, the second data, the third data, and the fourth data, the fifth voltage being higher than the first voltage, the fifth voltage being lower than the fourth voltage,   the controller is configured to send a first command to the semiconductor memory, and   in response to the first command, the semiconductor memory is configured to apply a sixth voltage to the second word line to read data from the second memory cell, apply a seventh voltage to the first word line to read a fifth data from the first memory cell after applying the sixth voltage to the first word line, the seventh voltage being based on the fifth voltage, and send the fifth data to the controller.   
     
     
         20 . The memory system of  claim 19 , wherein
 the semiconductor memory is configured to apply an eighth voltage within a second range to the first word line to read the fifth data from the first memory cell after applying the seventh voltage to the first word line.   
     
     
         21 . The memory system of  claim 20 , wherein
 the controller is configured to send a second command to the semiconductor memory, and   in response to the second command, the semiconductor memory is configured to apply a ninth voltage between the first range and the second range to the first word line to read a sixth data.   
     
     
         22 . The memory system of  claim 21 , wherein
 the semiconductor memory is configured to:   read a seventh data from the first plurality of memory cells by applying the first voltage to the first word line,   generate the first data based on the sixth data and the seventh data,   read an eighth data from the first plurality of memory cells by applying the second voltage to the first word line,   generate the second data based on the sixth data and the eighth data,   read a ninth data from the first plurality of memory cells by applying the third voltage to the first word line,   generate the third data based on the sixth data and the ninth data,   read a tenth data from the first plurality of memory cells by applying the fourth voltage to the first word line, and   generate the fourth data based on the sixth data and the tenth data.   
     
     
         23 . The memory system of  claim 22 , wherein
 the semiconductor memory includes a latch circuit, and   the semiconductor memory is configured to:   store the sixth data to the latch circuit, and   generate the first data based on the sixth data stored in the latch circuit and the seventh data.   
     
     
         24 . The memory system of  claim 19 , wherein
 the controller is configured to send a third command to the semiconductor memory,   the semiconductor memory is configured to, in response to the third command, send an eleventh data read from the first plurality of memory cells to the controller, and   the controller is configured to execute error correction processing of the eleventh data.   
     
     
         25 . The memory system of  claim 24 , wherein
 the controller is configured to send a fourth command for reading the first to fourth data to the semiconductor memory when the error correction processing of the eleventh data fails.   
     
     
         26 . The memory system of  claim 19 , wherein
 data stored in each of the first plurality of memory cells and the second plurality of memory cells corresponds to a threshold voltage of a plurality of threshold voltages, and   the semiconductor memory is configured to:   when applying the sixth voltage to the second word line, apply a tenth voltage higher than the plurality of threshold voltages to the first word line, and   when applying the seventh voltage to the first word line, apply an eleventh voltage higher than the plurality of threshold voltages to the second word line.   
     
     
         27 . The memory system of  claim 26 , wherein
 the semiconductor memory is configured to:   in response to the first command, apply a twelfth voltage to the second word line after applying the sixth voltage to the second word line, the twelfth voltage being higher than the sixth voltage, the twelfth voltage being lower than the tenth voltage, and   apply the seventh voltage to the first word line after applying the twelfth voltage to the second word line.   
     
     
         28 . The memory system of  claim 27 , wherein
 the semiconductor memory is configured to, when applying the twelfth voltage to the second word line, apply the tenth voltage to the first word line.   
     
     
         29 . The memory system of  claim 28 , wherein
 each of the first plurality of memory cells is capable of storing three-bit data, and   each of the second plurality of memory cells is capable of storing three-bit data.   
     
     
         30 . The memory system of  claim 29 , wherein
 the semiconductor memory is configured to, when applying the seventh voltage to the first word line, apply a thirteenth voltage higher than the eleventh voltage to the second word line after applying the eleventh voltage to the second word line.   
     
     
         31 . The memory system of  claim 30 , wherein
 the semiconductor memory is configured to, when applying the seventh voltage to the first word line, apply a fourteenth voltage higher than the thirteenth voltage to the second word line after applying the thirteenth voltage to the second word line.   
     
     
         32 . The memory system of  claim 31 , wherein
 the semiconductor memory includes a latch circuit,   the semiconductor memory is configured to, when data stored in the second memory cell is a value corresponding to a third range, read data from the first memory cell during which the eleventh voltage is applied to the second word line and store the read data to the latch circuit.   
     
     
         33 . The memory system of  claim 32 , wherein
 the semiconductor memory is configured to, when data in the second memory cell is a value corresponding to the third range, read a twelfth data from the first memory cell during which the eleventh voltage is applied to the second word line and generate the fifth data based on the twelfth data.   
     
     
         34 . The memory system of  claim 33 , wherein
 the semiconductor memory is configured to, when the data in the second memory cell is a value corresponding to a fourth range higher than the third range, read a thirteenth data from the first memory cell during which the eleventh voltage is applied to the second word line and generate the fifth data based on the thirteenth data.   
     
     
         35 . The memory system of  claim 34 , wherein
 the semiconductor memory is configured to, when the data in the second memory cell is a value corresponding to a fifth range higher than the fourth range, read a fourteenth data from the first memory cell during which the eleventh voltage is applied to the second word line and generate the fifth data based on the fourteenth data.